The acronym SerDes to many of you will sound like coming from another world, we are going extraterrestrial language, but they are really found in all types of hardware today and are one of the most used pieces of internal communication between the components of a processor, as well as external communication with other components. But what is it, how does it work, and where is this piece of hardware used?
On the PC, various interfaces communicate with each other with the CPU, APU, or GPU. But what is the piece that unifies the different signals that enter and leave a processor? We explain what this common piece is found in all hardware and how it works. Which is commonly called SerDes.
What is a SerDes?
SerDes have their origin in the world of telecommunications. The reason for its existence is quite simple, sending data through a single cable instead of several at the same time reduces the complexity of the internal intercom of a telecommunications network. Now if we think about it, the way in which the different logic and memory parts of both a processor and a system are communicated is through a series of cables.
At first glance, in terms of performance, it may seem that using a parallel interface is always much better, but there are a number of factors that make serial interfaces better. Which are? First of all, parallel interfaces take up much more space and are more susceptible to electromagnetic, apart from consuming more at the same clock speed. The disadvantage of serial interfaces is that they have a higher latency in sending data.
However, in a hardware design there are parts with a serial interface and others with a parallel interface. How to connect them to each other their communication interfaces are different? Well, with a SerDes, whose main job is to communicate various elements, especially peripherals with the CPU.
All roads lead to Rome
Take a look at your PC and the different interfaces for internal components and external peripherals. We have interfaces like SATA, PCI Express, USB and a long etcetera. Each of them has interfaces for different types of peripherals. Well, internally, each of these interfaces does not connect directly to the central processor hub, but rather to a series of SerDES.
Not surprisingly, there are different input and output interfaces for peripherals of all kinds that are designed to interact with the standard specifications of the different SerDes. What are those interfaces? Well, we have the case of the PCI Express interfaces in their different technologies, for storage such as SATA and SAS, for video transmission such as DisplayPort and HDMI, for networks such as the different gigabit ethernet interfaces, and so on. But, the thing is not limited only to I / O interfaces for peripherals and components, but the thing goes further and the RAM memory also communicates through a SERDES with the central hub that each processor has, known as Northbridge and that is in charge of communicating the different elements with each other and each one of them with the RAM memory.
Therefore, the different interfaces not only when designing, but also evolving, must take into account the evolution of SerDes at that very moment, since these interfaces will be connected to these in the internal logic of each integrated circuit. It must be taken into account that internally in a processor if there are too many interconnections then the complexity of the intercommunication will be too great. So it is best to reduce the number of interconnections by serializing the incoming data in exchange for increasing the clock speed.
How does a SerDes work?
If we take into account this pure and hard definition then a SerDes is still a piece of hardware composed of a multiplexer and a demultiplexer, which are two types of basic combinational systems. What a multiplexer or MUX does is convert a single signal into several different signals and a demultiplexer or DEMUX does the opposite task.
The difference is that the SerDES take into account the clock speed, since depending on when the data is transmitted, the interpretation by the processor is one or the other. In other words, when a data request is made from any component of a hardware system, there are times and therefore a window of opportunity to transmit the data. What does this translate into? Well, the data is transmitted following a time and therefore this implies a clock signal.
Suppose we want to serialize a parallel signal that is transmitted through a series of Full Duplex lines, which transmit 1 bit of information in each direction. The bandwidth is 1.25 Gbps, so this means that each of the lines works at 625 MHz. We have four lines in total, so if we serialize the signal then we will be talking about a signal at 5 Gbps, which in the The case of a Full Duplex line required the serial interface to operate at 2.5 GHZ. The reverse path is therefore easy to understand, we can make the 5 Gbps signal be transmitted through two lines using a speed of 1.25 GHz for each line, through four lines using a clock speed of 625 MHz each, and so on.
The evolution of the SerDes
Before we have commented how SerDES completely influence the design of future input and output interfaces, which implies that the development of future interfaces or evolutions of existing ones depends entirely on the SerDes to which they are connected, since that they must be able to communicate with them. For example, SerDES at 112 Gbps, the fastest to date on the market, use PAM4 signaling, hence this type of signaling is sounding for interfaces such as the future PCI Express 6.0.
However, advancing the communication speed of the SerDes is not an easy task, with each new generation in which the communication bandwidth is increased, new challenges appear, especially with those elements that degrade the quality of the signal that is transmit. Also we cannot forget that the voltage is not scaling in the same way as the clock speed, which causes the power consumption of the interfaces to skyrocket. Hence the adoption of PAM4 interfaces to avoid increasing the clock speed to limits that would not be acceptable.
At the moment only the GDDR6X memory in the NVIDIA RTX 30 uses a PAM4 interface, which means that the internal SerDes in these GPUs uses this type of interface to communicate with the GPU. Which influences the rest of the I / O interfaces of these GPUs. At the same time, this complicates the adoption of a PAM4 system in other systems, since it means that the interfaces have to adapt to the time rules of the SerDes included in the processor.
