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TE-151: Electrical Circuit Analysis

Here are detailed study notes for TE-151: Electrical Circuit Analysis, written from an Electrical/Computer Engineering perspective. These notes cover the fundamental principles of electrical circuit analysis—basic concepts, circuit laws, network theorems, transient analysis, AC steady-state analysis, resonance, and network parameters. The emphasis is on developing systematic problem-solving skills for analyzing linear electrical circuits.

1. Introduction to Electrical Circuits

1.1. What is Circuit Analysis?

Circuit Analysis is the process of determining voltages across and currents through each element in an electrical network. It applies fundamental laws and mathematical techniques to solve for unknown electrical quantities.

The Core Question: Given an electrical network with sources and passive elements, how do we systematically determine all voltages and currents?

1.2. Basic Electrical Quantities

Quantity	Symbol	Unit	Symbol	Definition
Charge	Q	Coulomb	C	∫ i dt
Current	I	Ampere	A	dQ/dt
Voltage	V	Volt	V	dW/dQ
Resistance	R	Ohm	Ω	V/I
Conductance	G	Siemens	S	1/R
Capacitance	C	Farad	F	Q/V
Inductance	L	Henry	H	λ/I
Power	P	Watt	W	VI
Energy	W	Joule	J	∫ P dt

1.3. Circuit Elements

Active Elements (Sources):

Element	Symbol	Characteristic	Unit
Independent Voltage Source	—○—○—	V = constant	V
Independent Current Source	—○—○—	I = constant	A
Dependent Voltage Source	—○—○— (diamond)	V = k × (other quantity)	V
Dependent Current Source	—○—○— (diamond)	I = k × (other quantity)	A

Passive Elements:

Element	Symbol	V-I Relationship	Unit
Resistor	—///—	V = IR	Ω
Capacitor	—		—	I = C dV/dt	F
Inductor	—○○○—	V = L dI/dt	H

Types of Dependent Sources:

Type	Symbol	Relationship
Voltage-Controlled Voltage Source (VCVS)	Diamond	V = μ V_x
Current-Controlled Voltage Source (CCVS)	Diamond	V = r I_x
Voltage-Controlled Current Source (VCCS)	Diamond	I = g V_x
Current-Controlled Current Source (CCCS)	Diamond	I = β I_x

1.4. Passive Sign Convention

   I → 
   ┌───┐
   │   │
   +   ─
   │   │
   └───┘
    V

Power absorbed: P = +VI (current enters positive terminal)
Power delivered: P = -VI (current leaves positive terminal)

2. Basic Circuit Laws

2.1. Ohm’s Law

The fundamental relationship between voltage, current, and resistance:

$V = I R$ $I = R V$ $R = I V$

2.2. Kirchhoff’s Laws

Kirchhoff’s Current Law (KCL):
The algebraic sum of currents entering a node is zero.

$k = 1 \sum n I_{k} = 0$

Equivalently: Sum of currents entering = sum of currents leaving.

Kirchhoff’s Voltage Law (KVL):
The algebraic sum of voltages around any closed loop is zero.

$k = 1 \sum n V_{k} = 0$

2.3. Series Circuits

R1 ── R2 ── R3

Property	Formula
Total Resistance	$R_{T} = R_{1} + R_{2} + R_{3}$
Current	$I_{T} = I_{1} = I_{2} = I_{3}$
Voltage Division	$V_{x} = V_{T} \times R ^{T} R ^{x}$
Power	$P_{T} = P_{1} + P_{2} + P_{3}$

2.4. Parallel Circuits

    ┌─ R1 ─┐
    ├─ R2 ─┤
    └─ R3 ─┘

Property	Formula
Total Conductance	$G_{T} = G_{1} + G_{2} + G_{3}$
Total Resistance	$R ^{T} 1 = R ^{1} 1 + R ^{2} 1 + R ^{3} 1$
Voltage	$V_{T} = V_{1} = V_{2} = V_{3}$
Current Division	$I_{x} = I_{T} \times R ^{x} R ^{T} = I_{T} \times G ^{T} G ^{x}$
Power	$P_{T} = P_{1} + P_{2} + P_{3}$

2.5. Series-Parallel Circuits

Simplify step by step:

Identify series and parallel combinations
Combine parallel resistors first or series first
Reduce to a single equivalent resistance
Work backward to find individual voltages and currents

3. Circuit Analysis Methods

3.1. Mesh Analysis (Loop Current Method)

Mesh analysis applies KVL to independent meshes.

Steps:

Identify independent meshes (closed loops with no other loops inside)
Assign mesh currents (clockwise direction)
Apply KVL to each mesh
Solve simultaneous equations for mesh currents
Determine branch currents from mesh currents

Mesh Equation (General form for mesh i):

$\sum R_{ii} I_{i} - \sum R_{ij} I_{j} = \sum V_{s i}$

Where:

$R_{ii}$ = sum of resistances in mesh i
$R_{ij}$ = common resistances between meshes i and j
$I_{j}$ = mesh current in adjacent mesh j
$\sum V_{s i}$ = sum of voltage sources in mesh i

Example (2 meshes):

$[R^{1} + R^{2} - R^{2} - R^{2} R^{2} + R^{3}] [I^{1} I^{2}] = [V^{1} - V^{2}]$

3.2. Nodal Analysis (Node Voltage Method)

Nodal analysis applies KCL to independent nodes.

Steps:

Select reference node (ground, assign V = 0)
Assign node voltages (V₁, V₂, …) to remaining nodes
Apply KCL at each non-reference node
Solve simultaneous equations for node voltages
Determine branch voltages and currents from node voltages

Nodal Equation (General form for node i):

$\sum G_{ii} V_{i} - \sum G_{ij} V_{j} = \sum I_{s i}$

Where:

$G_{ii}$ = sum of conductances connected to node i
$G_{ij}$ = conductances between nodes i and j
$V_{j}$ = voltage at adjacent node j
$\sum I_{s i}$ = sum of current sources entering node i

Example (2 nodes):

$[G^{1} + G^{2} - G^{2} - G^{2} G^{2} + G^{3}] [V^{1} V^{2}] = [I^{1} - I^{2}]$

3.3. Mesh vs. Nodal Analysis

Aspect	Mesh Analysis	Nodal Analysis
Variables	Mesh currents	Node voltages
Number of equations	$b - n + 1$	$n - 1$
Best for	Fewer meshes than nodes	Fewer nodes than meshes
Voltage sources	Easy	Convert to current sources
Current sources	Convert to voltage sources	Easy
Dependent sources	Can be handled	Can be handled

Where:

$n$ = number of nodes
$b$ = number of branches

4. Network Theorems

4.1. Superposition Theorem

In a linear network with multiple independent sources, the response (voltage or current) is the sum of responses from each source acting alone.

Procedure:

Consider one source at a time
Deactivate other sources:
- Voltage sources → short circuit (0V)
- Current sources → open circuit (0A)
Calculate response from active source
Repeat for each source
Sum all responses (consider polarity/direction)

Limitations: Only for linear circuits (resistors, capacitors, inductors, linear dependent sources)

4.2. Thevenin’s Theorem

Any linear two-terminal network can be replaced by an equivalent voltage source $V_{T h}$ in series with a resistance $R_{T h}$ .

Procedure:

Remove the load resistor (where $V_{T h}$ is measured)
Calculate $V_{T h}$ = open-circuit voltage at terminals
Calculate $R_{T h}$ :
- Deactivate all independent sources (voltage sources shorted, current sources opened)
- Find equivalent resistance looking into terminals
Draw Thevenin equivalent circuit: $V_{T h}$ in series with $R_{T h}$

For circuits with dependent sources:

$R_{T h} = V_{oc} / I_{sc}$
Apply test voltage/current to find resistance

4.3. Norton’s Theorem

Any linear two-terminal network can be replaced by an equivalent current source $I_{N}$ in parallel with a resistance $R_{N}$ .

Procedure:

Remove the load resistor
Calculate $I_{N}$ = short-circuit current at terminals
Calculate $R_{N}$ (same as $R_{T h}$ )
Draw Norton equivalent circuit: $I_{N}$ in parallel with $R_{N}$

Relationships:

$V_{T h} = I_{N} \cdot R_{N}$ $R_{T h} = R_{N}$ $I_{N} = R ^{T h} V ^{T h} = I_{sc}$

4.4. Maximum Power Transfer Theorem

Maximum power is transferred from a source to a load when the load resistance equals the Thevenin resistance.

$R_{L} = R_{T h}$

Maximum Power:

$P_{m a x} = 4 R ^{T h} V ^{T h 2}$

Efficiency at maximum power: 50%

4.5. Millman’s Theorem

For multiple voltage sources in parallel with series resistances:

$V_{e q} = \sum R ^{i} 1 \sum R ^{i} V ^{i}$ $R_{e q} = \sum R ^{i} 1 1$

4.6. Substitution Theorem

Any branch in a network can be replaced by an equivalent branch that maintains the same voltage and current.

4.7. Reciprocity Theorem

In a linear passive network, the ratio of response to excitation is unchanged if the positions of the source and response are interchanged.

4.8. Tellegen’s Theorem

For any network, the sum of power across all branches is zero.

$k = 1 \sum b v_{k} i_{k} = 0$

5. Capacitors and Inductors

5.1. Capacitors

Capacitors store energy in an electric field.

Capacitance:

$C = V Q$

Current-Voltage Relationship:

$i_{C} = C d t d v ^{C}$ $v_{C} = C 1 \int i_{C} d t + v_{C} (0)$

Energy Stored:

$W_{C} = 21 C V^{2} = 21 C Q ^{2}$

Capacitors in Series:

$C ^{T} 1 = C ^{1} 1 + C ^{2} 1 + C ^{3} 1$

Capacitors in Parallel:

$C_{T} = C_{1} + C_{2} + C_{3}$

5.2. Inductors

Inductors store energy in a magnetic field.

Inductance:

$L = I λ$

Voltage-Current Relationship:

$v_{L} = L d t d i ^{L}$ $i_{L} = L 1 \int v_{L} d t + i_{L} (0)$

Energy Stored:

$W_{L} = 21 L I^{2}$

Inductors in Series:

$L_{T} = L_{1} + L_{2} + L_{3}$

Inductors in Parallel:

$L ^{T} 1 = L ^{1} 1 + L ^{2} 1 + L ^{3} 1$

5.3. Duality

Capacitors and inductors are dual elements:

Capacitor	Inductor
$i = C d t d v$	$v = L d t d i$
$v = C 1 \int i d t$	$i = L 1 \int v d t$
Series: $1/ C_{T} = \sum 1/ C_{i}$	Series: $L_{T} = \sum L_{i}$
Parallel: $C_{T} = \sum C_{i}$	Parallel: $1/ L_{T} = \sum 1/ L_{i}$
$W = 2 1 C V^{2}$	$W = 2 1 L I^{2}$

6. Transient Analysis

6.1. First-Order Circuits

RC Circuit (Charging):

$v_{C} (t) = V_{f} + (V_{i} - V_{f}) e^{- t / τ}$ $τ = RC$

RC Circuit (Discharging):

$v_{C} (t) = V_{0} e^{- t / τ}$

RL Circuit (Current build-up):

$i_{L} (t) = I_{f} + (I_{i} - I_{f}) e^{- t / τ}$ $τ = R L$

RL Circuit (Current decay):

$i_{L} (t) = I_{0} e^{- t / τ}$

6.2. General Solution for First-Order Circuits

$y (t) = y (\infty) + [y (0^{+}) - y (\infty)] e^{- t / τ}$

Where:

$y (t)$ = voltage or current
$y (0^{+})$ = initial value (just after t=0)
$y (\infty)$ = final value (steady-state)
$τ$ = time constant

6.3. Time Constant Significance

Time	Percentage of Final
$τ$	63.2%
$2 τ$	86.5%
$3 τ$	95.0%
$4 τ$	98.2%
$5 τ$	99.3%

6.4. Second-Order Circuits (RLC)

Series RLC Circuit:

$L d t d i + R i + C 1 \int i d t = v_{s} (t)$

Differential Equation:

$d t ^{2} d ^{2} i + L R d t d i + L C 1 i = L 1 d t d v ^{s}$

Characteristic Equation:

$s^{2} + L R s + L C 1 = 0$

Roots:

$s_{1, 2} = - α \pm α^{2} - ω^{02}$

Where:

$α = 2 L R$ = damping factor (neper frequency)
$ω_{0} = L C 1$ = resonant frequency

6.5. Response Types

Case	Condition	Damping	Response Form
Overdamped	$α > ω_{0}$	High	$y (t) = A_{1} e^{s 1 t} + A_{2} e^{s 2 t}$
Critically damped	$α = ω_{0}$	Critical	$y (t) = (A_{1} + A_{2} t) e^{- α t}$
Underdamped	$α < ω_{0}$	Low	$y (t) = e^{- α t} (A_{1} cos ω_{d} t + A_{2} sin ω_{d} t)$

Where $ω_{d} = ω^{02} - α^{2}$ = damped natural frequency

6.6. Initial and Final Conditions

Capacitor:

$v_{C} (0^{-}) = v_{C} (0^{+})$ (voltage continuous)
Capacitor behaves as voltage source at t=0⁺
Capacitor behaves as open circuit at t=∞

Inductor:

$i_{L} (0^{-}) = i_{L} (0^{+})$ (current continuous)
Inductor behaves as current source at t=0⁺
Inductor behaves as short circuit at t=∞

6.7. Step Response of RLC Circuit

For underdamped case:

$v_{C} (t) = V_{f} + e^{- α t} (A_{1} cos ω_{d} t + A_{2} sin ω_{d} t)$

7. Sinusoidal Steady-State Analysis

7.1. Sinusoidal Waveforms

$v (t) = V_{m} sin (ω t + ϕ)$

Where:

$V_{m}$ = amplitude (peak value)
$ω = 2 π f$ = angular frequency (rad/s)
$f$ = frequency (Hz)
$T = 1/ f = 2 π / ω$ = period (s)
$ϕ$ = phase angle (rad)

7.2. Phase Relationships

Relationship	Phase Difference
In phase	0°
Current lags voltage	$ϕ > 0$ (inductive)
Current leads voltage	$ϕ < 0$ (capacitive)

7.3. RMS Values

$V_{r m s} = T 1 \int^{0 T} v^{2} (t) d t$

For sinusoid:

$V_{r m s} = 2 V ^{m} \approx 0.707 V_{m}$ $I_{r m s} = 2 I ^{m} \approx 0.707 I_{m}$

7.4. Phasor Representation

A phasor is a complex number representing the magnitude and phase of a sinusoid.

$V = V_{r m s} ∠ ϕ = V_{r m s} e^{j ϕ}$

Time-domain to Phasor:

$v (t) = V_{m} sin (ω t + ϕ) \to V = 2 V ^{m} ∠ ϕ$

Phasor to Time-domain:

$V = V ∠ ϕ \to v (t) = 2 V sin (ω t + ϕ)$

7.5. Impedance

Impedance is the AC equivalent of resistance.

$Z = I V = R + j X$ $∣ Z ∣ = R^{2} + X^{2}$ $θ = tan^{-1} (R X)$

Element Impedances:

Element	Impedance	Phase	Magnitude
Resistor	$Z_{R} = R$	0°	R
Inductor	$Z_{L} = jω L$	+90°	$ω L$
Capacitor	$Z_{C} = jω C 1 = - j ω C 1$	-90°	$1/ (ω C)$

7.6. Admittance

$Y = Z 1 = G + j B$

Element Admittances:

Element	Admittance	Phase
Resistor	$Y_{R} = G = 1/ R$	0°
Inductor	$Y_{L} = jω L 1 = - j ω L 1$	-90°
Capacitor	$Y_{C} = jω C$	+90°

7.7. Phasor Analysis Procedure

Convert time-domain sources to phasors
Replace elements with impedances (or admittances)
Solve using DC circuit analysis techniques (KVL, KCL, mesh, nodal, Thevenin)
Convert phasor results back to time-domain

KCL in Phasor Form:

$\sum I_{k} = 0$

KVL in Phasor Form:

$\sum V_{k} = 0$

Ohm’s Law in Phasor Form:

$V = IZ$

7.8. Impedance Combinations

Series:

$Z_{e q} = Z_{1} + Z_{2} + Z_{3}$

Parallel:

$Z ^{e q} 1 = Z ^{1} 1 + Z ^{2} 1 + Z ^{3} 1$

8. AC Power Analysis

8.1. Instantaneous Power

$p (t) = v (t) i (t) = V_{m} I_{m} sin (ω t + θ_{v}) sin (ω t + θ_{i})$

8.2. Average Power (Real Power)

$P = T 1 \int_{0 T} p (t) d t = V_{r m s} I_{r m s} cos (θ_{v} - θ_{i})$ $P = V_{r m s} I_{r m s} cos ϕ$

Where $ϕ = θ_{v} - θ_{i}$ = power factor angle

Units: Watts (W)

8.3. Reactive Power

$Q = V_{r m s} I_{r m s} sin (θ_{v} - θ_{i}) = V_{r m s} I_{r m s} sin ϕ$

Units: Volt-Ampere Reactive (VAR)

For inductors: $Q_{L} = I_{r m s 2} X_{L} = V_{r m s 2} / X_{L}$ (positive, lagging)
For capacitors: $Q_{C} = - I_{r m s 2} X_{C} = - V_{r m s 2} / X_{C}$ (negative, leading)

8.4. Apparent Power

$S = V_{r m s} I_{r m s} = P^{2} + Q^{2}$

Units: Volt-Ampere (VA)

8.5. Power Factor

$PF = S P = cos ϕ$

Lagging PF: Inductive load (Q > 0, current lags voltage)
Leading PF: Capacitive load (Q < 0, current leads voltage)
Unity PF: Resistive load (Q = 0)

8.6. Complex Power

$S = V I^{*} = P + j Q$ $S = V_{r m s} I_{r m s} ∠ (θ_{v} - θ_{i}) = V_{r m s} I_{r m s} cos ϕ + j V_{r m s} I_{r m s} sin ϕ$

8.7. Power Triangle

        S
       /|
      / |
     /  |
    /   | Q
   /    |
  /φ    |
 /______|
    P

8.8. Power Factor Correction

Adding capacitors in parallel to inductive loads to improve power factor.

Required reactive power compensation:

$Q_{C} = P (tan ϕ_{1} - tan ϕ_{2})$

Required capacitance:

$C = ω V ^{r m s 2} Q ^{C}$

9. Resonance

9.1. Series Resonance

Resonant frequency:

$ω_{0} = L C 1, f_{0} = 2 π L C 1$

At resonance:

$X_{L} = X_{C}$ (impedance is purely resistive)
$Z = R$ (minimum impedance)
$I = V / R$ (maximum current)
$V_{L} = V_{C}$ (equal magnitude, opposite phase)

Quality Factor (Q):

$Q = R ω ^{0} L = ω ^{0} RC 1 = R 1 C L$

Bandwidth:

$B W = Q ω ^{0} = L R$

Half-Power Frequencies:

$ω_{1, 2} = ω_{0} (1 + 4 Q ^{2} 1 \pm 2 Q 1)$

For high Q: $ω_{1, 2} \approx ω_{0} \pm 2 B W$

9.2. Parallel Resonance

Resonant frequency:

$ω_{0} = L C 1$

At resonance:

$X_{L} = X_{C}$
$Z = L / (RC)$ (maximum impedance)
$I = V / Z$ (minimum current)

Quality Factor:

$Q = R L C = ω ^{0} L R = ω_{0} RC$

Bandwidth:

$B W = Q ω ^{0} = RC 1$

10. Frequency Response

10.1. Transfer Function

$H (jω) = X ( jω ) Y ( jω )$

Where:

$X (jω)$ = input phasor
$Y (jω)$ = output phasor

10.2. Magnitude and Phase Response

$∣ H (jω) ∣ = magnitude response$ $∠ H (jω) = phase response$

10.3. Bode Plots

Magnitude Plot: $20 log_{10} ∣ H (jω) ∣$ (dB) vs. $log_{10} ω$

Phase Plot: $∠ H (jω)$ vs. $log_{10} ω$

First-Order Factor $(1 + jω / ω_{c})$ :

Low frequency: 0 dB
High frequency: +20 dB/decade
Corner frequency: $ω_{c}$ , -45° phase

First-Order Factor $1/ (1 + jω / ω_{c})$ :

Low frequency: 0 dB
High frequency: -20 dB/decade
Corner frequency: $ω_{c}$ , +45° phase

Second-Order Factor:

Peak at resonance for $ζ < 0.707$
Peak magnitude = $20 log_{10} (1/2 ζ)$ dB

11. Summary Table: Key Equations

Equation	Description
$V = I R$	Ohm’s law
$\sum I = 0$	KCL
$\sum V = 0$	KVL
$R_{T} = R_{1} + R_{2} + \dots$	Series resistance
$1/ R_{T} = 1/ R_{1} + 1/ R_{2} + \dots$	Parallel resistance
$y (t) = y (\infty) + [y (0^{+}) - y (\infty)] e^{- t / τ}$	First-order transient
$τ = RC$	RC time constant
$τ = L / R$	RL time constant
$s^{2} + (R / L) s + 1/ L C = 0$	RLC characteristic equation
$V = IZ$	Ohm’s law (phasor)
$S = V I^{*} = P + j Q$	Complex power
$f_{0} = 1/ (2 π L C)$	Resonant frequency
$Q = (1/ R) L / C$	Series RLC quality factor

12. Standard Textbooks

Author	Title	Focus
Alexander & Sadiku	Fundamentals of Electric Circuits	Comprehensive
Nilsson & Riedel	Electric Circuits	Classic
Hayt, Kemmerly & Durbin	Engineering Circuit Analysis	Problem-solving
Irwin & Nelms	Basic Engineering Circuit Analysis	Practical

13. Final Study Checklist

Topic	Key Skills
Basic Laws	Apply Ohm’s law, KCL, KVL
Series/Parallel	Simplify resistor networks; use voltage/current division
Mesh/Nodal Analysis	Write and solve simultaneous equations
Network Theorems	Apply superposition, Thevenin, Norton, maximum power
Capacitors/Inductors	Calculate equivalent C and L; understand V-I relationships
Transient Analysis	Solve first and second order circuits; find time constants
Phasor Analysis	Convert to phasors; calculate impedances; solve AC circuits
AC Power	Calculate P, Q, S, PF; perform PF correction
Resonance	Calculate resonant frequency, Q, bandwidth
Frequency Response	Sketch Bode plots; interpret magnitude/phase

TE-251 Digital Logic Design – Detailed Study Notes

These study notes are designed for undergraduate engineering students taking a course in Digital Logic Design. The notes cover the fundamental principles of number systems, Boolean algebra, logic gates, combinational and sequential circuits, and digital system design.

1. Introduction to Digital Logic Design

1.1 Analog vs. Digital Signals

Aspect	Analog	Digital
Signal type	Continuous	Discrete (0 and 1)
Range	Infinite values	Two values (HIGH/LOW)
Noise immunity	Low	High
Storage	Difficult	Easy
Examples	Temperature, sound	Computer data, logic circuits

1.2 Digital Logic Levels

Logic Family	LOW (0) Voltage	HIGH (1) Voltage
TTL (Transistor-Transistor Logic)	0 – 0.8 V	2.0 – 5.0 V
CMOS (Complementary MOS)	0 – 1.5 V	3.5 – 5.0 V
LVTTL (3.3V)	0 – 0.4 V	2.4 – 3.3 V

1.3 Number Systems

System	Base	Digits	Example
Binary	2	0, 1	1011₂
Octal	8	0-7	17₈
Decimal	10	0-9	255₁₀
Hexadecimal	16	0-9, A-F	FF₁₆

1.4 Number System Conversions

Binary to Decimal:

1011₂ = 1×2³ + 0×2² + 1×2¹ + 1×2⁰ = 8 + 0 + 2 + 1 = 11₁₀

Decimal to Binary (Repeated division by 2):

13 ÷ 2 = 6 remainder 1 (LSB)
6 ÷ 2 = 3 remainder 0
3 ÷ 2 = 1 remainder 1
1 ÷ 2 = 0 remainder 1 (MSB)
Result: 1101₂

Binary to Hexadecimal (Group of 4 bits):

1011 1100₂ = BC₁₆ (B=11, C=12)

Hexadecimal to Binary:

A3₁₆ = 1010 0011₂

1.5 Binary Arithmetic

Operation	Example
Addition	0+0=0, 0+1=1, 1+0=1, 1+1=0 carry 1
Subtraction	0-0=0, 1-0=1, 1-1=0, 0-1=1 borrow 1
Multiplication	Shift and add
Division	Repeated subtraction

1.6 Complement Representations

1’s Complement: Invert all bits

Binary: 1011 → 1's complement: 0100

2’s Complement: 1’s complement + 1

Binary: 1011 → 1's: 0100 → 2's: 0101

Range of n-bit signed numbers:

Signed magnitude: -(2ⁿ⁻¹ – 1) to +(2ⁿ⁻¹ – 1)
1’s complement: -(2ⁿ⁻¹ – 1) to +(2ⁿ⁻¹ – 1)
2’s complement: -2ⁿ⁻¹ to +(2ⁿ⁻¹ – 1) (most common)

2. Boolean Algebra and Logic Gates

2.1 Basic Logic Gates

Gate	Symbol	Boolean Expression	Truth Table	Equivalent Circuit
NOT (Inverter)	──o──	Y = ¬A = A’	0→1, 1→0
AND	┌─┐	Y = A·B	00→0, 01→0, 10→0, 11→1	Series switches
OR	┌─┐	Y = A+B	00→0, 01→1, 10→1, 11→1	Parallel switches
NAND	AND + NOT	Y = (A·B)’	00→1, 01→1, 10→1, 11→0	Universal gate
NOR	OR + NOT	Y = (A+B)’	00→1, 01→0, 10→0, 11→0	Universal gate
XOR	┌─┐	Y = A⊕B	00→0, 01→1, 10→1, 11→0	Odd function
XNOR	XOR + NOT	Y = (A⊕B)’	00→1, 01→0, 10→0, 11→1	Equality

2.2 Boolean Algebra Laws

Law	Expression
Identity	A + 0 = A, A · 1 = A
Null	A + 1 = 1, A · 0 = 0
Idempotent	A + A = A, A · A = A
Complement	A + A’ = 1, A · A’ = 0
Involution	(A’)’ = A
Commutative	A + B = B + A, A · B = B · A
Associative	(A+B)+C = A+(B+C), (A·B)·C = A·(B·C)
Distributive	A·(B+C) = A·B + A·C, A + (B·C) = (A+B)·(A+C)
Absorption	A + A·B = A, A·(A+B) = A
DeMorgan’s	(A+B)’ = A’·B’, (A·B)’ = A’ + B’
Consensus	AB + A’C + BC = AB + A’C

2.3 Universal Gates (NAND and NOR)

Any logic gate can be constructed using only NAND gates or only NOR gates.

NAND as NOT:

NOT A = A NAND A

NAND as AND:

A AND B = (A NAND B) NAND (A NAND B)

NAND as OR:

A OR B = (A NAND A) NAND (B NAND B)

3. Boolean Function Minimization

3.1 Minterms and Maxterms

Term	Definition	Example (3 variables)
Minterm	Product term where each variable appears once (true or complemented)	m₀ = A’B’C’, m₁ = A’B’C, …, m₇ = ABC
Maxterm	Sum term where each variable appears once	M₀ = A+B+C, M₁ = A+B+C’, …, M₇ = A’+B’+C’

Relationship: m_i = M_i’

3.2 Sum of Products (SOP) and Product of Sums (POS)

Form	Expression	Example
SOP	OR of AND terms (minterms)	F = A’B + AB’C
POS	AND of OR terms (maxterms)	F = (A+B)(A’+C)

3.3 Karnaugh Maps (K-Maps)

2-Variable K-Map:

     B
    0   1
A 0 |m0|m1|
  1 |m2|m3|

3-Variable K-Map:

      BC
      00  01  11  10
A 0 |m0|m1|m3|m2|
  1 |m4|m5|m7|m6|

4-Variable K-Map:

        CD
        00  01  11  10
AB 00 |m0|m1|m3|m2|
   01 |m4|m5|m7|m6|
   11 |m12|m13|m15|m14|
   10 |m8|m9|m11|m10|

K-Map Minimization Rules:

Group adjacent 1’s in powers of 2 (1, 2, 4, 8, 16)
Larger groups = simpler terms
Groups can wrap around edges (top to bottom, left to right)
Each 1 must be in at least one group
Don’t care conditions (X) can be used as 0 or 1

3.4 Quine-McCluskey Tabular Method

Used for minimizing functions with many variables (≥5) where K-maps become impractical.

Steps:

List minterms in binary
Group by number of 1’s
Combine terms differing by one bit
Repeat until no further combination possible
Identify prime implicants
Form prime implicant table
Select essential prime implicants

3.5 Don’t Care Conditions

Definition: Input combinations that never occur (or outputs that don’t matter)

Use: Can be assigned 0 or 1 to simplify the expression

Representation: X or d

4. Combinational Logic Circuits

4.1 Adders

Half Adder (HA):
| Inputs | Outputs |

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Sum = A ⊕ B
Carry = A · B

Full Adder (FA):

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Sum = A ⊕ B ⊕ Cin
Cout = A·B + Cin·(A⊕B)

Ripple Carry Adder (RCA):

Multiple full adders connected in series
Carry propagates from LSB to MSB (slow)
Delay = n × t_FA

Carry Lookahead Adder (CLA):

Generates carries in parallel (fast)
Generate: G_i = A_i · B_i
Propagate: P_i = A_i ⊕ B_i
C_{i+1} = G_i + P_i·C_i
Delay = constant (independent of n)

4.2 Subtractors

Half Subtractor:

Difference = A ⊕ B
Borrow = A' · B

Full Subtractor:

Difference = A ⊕ B ⊕ Bin
Borrow = A'·B + A'·Bin + B·Bin

4.3 Comparators

1-bit Comparator:

A	B	A<B	A=B	A>B
0	0	0	1	0
0	1	1	0	0
1	0	0	0	1
1	1	0	1	0

n-bit Comparator:

Compare MSB first
Can be built using XOR gates and priority logic

4.4 Multiplexers (MUX)

Aspect	Detail
Definition	Selects one of many inputs to output
Select lines	n select lines for 2ⁿ inputs
2:1 MUX	Y = S’·I₀ + S·I₁
4:1 MUX	Y = S₁’S₀’I₀ + S₁’S₀I₁ + S₁S₀’I₂ + S₁S₀I₃

Using MUX to implement logic functions:

Connect variables to select lines
Connect constants (0,1) or variables to data inputs

4.5 Demultiplexers (DEMUX)

Aspect	Detail
Definition	Routes one input to one of many outputs
Select lines	n select lines for 2ⁿ outputs
1:2 DEMUX	Y₀ = S’·I, Y₁ = S·I
1:4 DEMUX	Four outputs based on select lines

4.6 Decoders

Aspect	Detail
Definition	Converts binary code to one active output
n-to-2ⁿ decoder	n inputs, 2ⁿ outputs
2-to-4 decoder	Outputs: Y₀ = A’A’, Y₁ = A’B, Y₂ = AB’, Y₃ = AB
Enable input	Activates decoder when enabled

4.7 Encoders

Aspect	Detail
Definition	Converts active input to binary code
Priority encoder	Encodes highest priority active input
4-to-2 priority encoder	Outputs binary code of highest priority input

4.8 Parity Generators/Checkers

Aspect	Detail
Even parity	Number of 1’s is even
Odd parity	Number of 1’s is odd
Parity generator	Adds parity bit to data
Parity checker	Verifies parity (detects single-bit errors)

4.9 Arithmetic Logic Unit (ALU)

Functions:

Arithmetic: ADD, SUB, INC, DEC
Logic: AND, OR, XOR, NOT
Shift: Left shift, right shift

n-bit ALU: Built from n 1-bit ALU slices (using full adders and logic gates)

5. Sequential Logic Circuits

5.1 Latches

SR Latch (NOR-based):

S	R	Q	Q’	State
0	0	Q	Q’	Hold
0	1	0	1	Reset
1	0	1	0	Set
1	1	0	0	Invalid

SR Latch (NAND-based):

Active low inputs: S’, R’

D Latch (Transparent latch):

E	D	Q(t+1)	Q'(t+1)
0	X	Q	Q’	(Hold)
1	0	0	1	(Store 0)
1	1	1	0	(Store 1)

5.2 Flip-Flops

Type	Characteristic Equation	Symbol	Triggering
D Flip-Flop	Q(t+1) = D	Edge-triggered	Rising/falling edge
JK Flip-Flop	Q(t+1) = J·Q’ + K’·Q	Edge-triggered	Rising/falling edge
T Flip-Flop	Q(t+1) = Q’ (toggle)	Edge-triggered	Rising/falling edge

JK Flip-Flop Truth Table:

J	K	Q(t+1)
0	0	Q (Hold)
0	1	0 (Reset)
1	0	1 (Set)
1	1	Q’ (Toggle)

T Flip-Flop from JK:

Connect J = K = T

D Flip-Flop from JK:

J = D, K = D’

5.3 Flip-Flop Timing Parameters

Parameter	Description
Setup time (t_su)	Minimum time input must be stable before clock edge
Hold time (t_h)	Minimum time input must be stable after clock edge
Propagation delay (t_p)	Time from clock edge to output change
Clock-to-Q delay (t_cq)	Same as propagation delay

5.4 Registers

Type	Description
Parallel register	Multiple D flip-flops with common clock
Shift register	Bits shift left/right on each clock
– SISO	Serial-in, serial-out
– SIPO	Serial-in, parallel-out
– PISO	Parallel-in, serial-out
– PIPO	Parallel-in, parallel-out
Universal shift register	Bidirectional, parallel load capability

5.5 Counters

Asynchronous (Ripple) Counters:

Flip-flops connected in series
Clock only to first flip-flop
Slower, simpler

Synchronous Counters:

All flip-flops receive same clock
Faster, more complex

Binary Counter:

Counts 0, 1, 2, …, 2ⁿ-1

BCD Counter (Decade Counter):

Counts 0, 1, 2, …, 9 then resets

Ring Counter:

Single 1 circulates
n states (n flip-flops)

Johnson Counter (Twisted Ring):

Complementary feedback
2n states (n flip-flops)

Counter Design Steps:

Draw state diagram
Create state table
Determine flip-flop inputs (using excitation tables)
Simplify input equations (K-maps)
Draw logic diagram

5.6 Excitation Tables

Current State	Next State	D	T	JK
0 → 0	0	0	0	0X
0 → 1	1	1	1	1X
1 → 0	0	0	1	X1
1 → 1	1	1	0	X0

6. Finite State Machines (FSM)

6.1 Types of FSMs

Type	Output	Depends on	Example
Moore	State only	Current state	Traffic light controller
Mealy	State + inputs	Current state and inputs	Sequence detector

6.2 FSM Design Steps

1. Problem statement
2. State diagram
3. State table
4. State assignment (binary, gray, one-hot)
5. Determine next state and output equations
6. Flip-flop input equations
7. Draw logic diagram

6.3 State Assignment Techniques

Method	Description	Number of Flip-Flops
Binary	Sequential binary numbers	⌈log₂n⌉
Gray code	Adjacent states differ by one bit	⌈log₂n⌉
One-hot	One flip-flop per state	n

6.4 Sequence Detector Example

Design a Mealy machine to detect sequence “101”:

State diagram:

S0 (0) --1--> S1 (0)
S1 --0--> S2 (0)
S2 --1--> S3 (1)  (output 1)
S3 --1--> S1
S3 --0--> S2
S1 --1--> S1
S2 --0--> S0

7. Memory and Programmable Logic

7.1 Memory Types

Type	Volatile	Read/Write	Speed	Use
SRAM	Yes	Read/Write	Fast	Cache
DRAM	Yes	Read/Write	Medium	Main memory
ROM	No	Read only	Medium	Firmware
PROM	No	Program once	Medium	Small volumes
EPROM	No	Erase (UV) + program	Medium	Prototyping
EEPROM	No	Erase (electrical) + program	Slow	Configuration
Flash	No	Read/Write (blocks)	Medium	SSDs, USB drives

7.2 Memory Organization

Address lines (n): 2ⁿ memory locations
Data lines (m): m bits per location
Total capacity: 2ⁿ × m bits

Example: 1K × 8 memory: 1024 addresses (10 address lines), 8 data lines

7.3 Programmable Logic Devices (PLDs)

Device	Gates	Flip-Flops	Programmability	Complexity
PROM	Fixed AND, programmable OR	No	One-time	Low
PLA	Programmable AND, programmable OR	No	One-time	Medium
PAL	Programmable AND, fixed OR	Yes (optional)	One-time	Medium
CPLD	Multiple PALs + interconnect	Yes	Reusable	High
FPGA	Configurable logic blocks + routing	Yes	Reusable	Very high

8. Sample Exam Questions

Short Answer (5 marks each)

Convert decimal 156 to binary, octal, and hexadecimal.
Simplify using Boolean algebra: F = A·B + A·B’ + A’·B
Distinguish between combinational and sequential logic circuits.
What is the difference between a latch and a flip-flop?
Distinguish between Moore and Mealy machines.

Numerical Problems (10-15 marks)

1. K-Map Simplification:
Simplify F(A,B,C,D) = Σ(0,2,5,7,8,10,13,15)

Solution:

K-map minimization yields:
F = B·D + B'·D' + A·C·D + A·C'·D'? (verify)

2. Counter Design:
Design a 3-bit synchronous binary counter using JK flip-flops.

Solution:

State table and excitation:
Q2 Q1 Q0 | Q2' Q1' Q0' | J2 K2 | J1 K1 | J0 K0
0 0 0 | 0 0 1 | 0 X | 0 X | 1 X
0 0 1 | 0 1 0 | 0 X | 1 X | X 1
0 1 0 | 0 1 1 | 0 X | X 0 | 1 X
0 1 1 | 1 0 0 | 1 X | X 1 | X 1
1 0 0 | 1 0 1 | X 0 | 0 X | 1 X
1 0 1 | 1 1 0 | X 0 | 1 X | X 1
1 1 0 | 1 1 1 | X 0 | X 0 | 1 X
1 1 1 | 0 0 0 | X 1 | X 1 | X 1

From K-maps:
J0 = 1, K0 = 1
J1 = Q0, K1 = Q0
J2 = Q1·Q0, K2 = Q1·Q0

Quick Revision Table – Logic Gates Summary

Gate	Symbol	Expression	Truth Table (A,B)
NOT	──o──	A’	0→1, 1→0
AND	&	A·B	00→0, 01→0, 10→0, 11→1
OR	≥1	A+B	00→0, 01→1, 10→1, 11→1
NAND	& with o	(A·B)’	00→1, 01→1, 10→1, 11→0
NOR	≥1 with o	(A+B)’	00→1, 01→0, 10→0, 11→0
XOR	=1	A⊕B	00→0, 01→1, 10→1, 11→0
XNOR	=1 with o	(A⊕B)’	00→1, 01→0, 10→0, 11→1

Quick Revision Table – Flip-Flop Comparison

Type	Characteristic Equation	Excitation Table
D	Q(t+1)=D	D=Q(t+1)
JK	Q(t+1)=JQ’+K’Q	J=Q(t+1), K=Q(t+1)’
T	Q(t+1)=Q’	T=Q⊕Q(t+1)

TE-259: Amplifiers & Oscillators – Comprehensive Study Notes

These notes provide a complete framework for Amplifiers & Oscillators, covering the fundamental principles, classifications, and design considerations for electronic circuits that increase signal power (amplifiers) and generate periodic waveforms (oscillators). The focus is on understanding the underlying theory, feedback mechanisms, stability criteria, and practical applications of these essential building blocks in electronic systems .

Part 1: Fundamentals of Amplifiers

1.1 What is an Amplifier?

An amplifier is an electronic device that increases the power, voltage, or current of a signal applied to its input. It is a fundamental building block in virtually all electronic systems, from audio equipment to wireless transmitters and sensor interfaces .

The amplification principle: A small input signal controls a larger output signal, with the additional power drawn from an external DC power supply.

1.2 Classification of Amplifiers

Amplifiers can be classified based on several criteria. The most fundamental classification is by the type of signal they amplify and their transfer characteristic .

1.2.1 By Transfer Characteristic (Type of Gain)

Amplifier Type	Input Signal	Output Signal	Gain Parameter	Unit	Typical Application
Voltage Amplifier	Voltage (V)	Voltage (V)	$A_{v} = V_{o u t} / V_{in}$	V/V or dB	General-purpose, audio preamplifiers
Current Amplifier	Current (I)	Current (I)	$A_{i} = I_{o u t} / I_{in}$	A/A or dB	Photodetector interfaces
Transconductance Amplifier	Voltage (V)	Current (I)	$G_{m} = I_{o u t} / V_{in}$	Siemens (S)	Operational transconductance amplifiers (OTAs)
Transresistance Amplifier	Current (I)	Voltage (V)	$R_{m} = V_{o u t} / I_{in}$	Ohms (Ω)	Photodiode amplifiers, I/V converters

1.2.2 By Frequency Range

Class	Frequency Range	Applications
DC Amplifier	0 Hz to tens of kHz	Sensor interfaces, instrumentation
Audio Amplifier	20 Hz to 20 kHz	Hi-Fi, public address systems
Video Amplifier	0 Hz to several MHz	Television, computer monitors
RF Amplifier	kHz to hundreds of GHz	Radio, wireless communications

1.2.3 By Conduction Angle (Power Amplifier Classes)

Class	Conduction Angle	Efficiency (Max)	Linearity	Applications
A	360° (always on)	25-50%	Excellent	High-fidelity audio, low-power RF
B	180° (push-pull)	78.5%	Good (crossover distortion)	Audio, some RF applications
AB	180°-360°	50-70%	Very Good	Most audio power amplifiers
C	<180°	80-90%	Poor	RF transmitters
D	Switching	90-95%	Good (with filtering)	Portable audio, subwoofers
E/F	Switching, tuned	>80%	Poor	RF power amplifiers

Part 2: Feedback in Amplifiers

2.1 The Feedback Concept

Feedback is the process of feeding a portion of the output signal back to the input. It is the most important concept in amplifier design, fundamentally determining stability, gain, and performance .

Basic Feedback Equation:

$A_{f} = 1 + A β A$

Where:

$A_{f}$ = Closed-loop gain (gain with feedback)
$A$ = Open-loop gain (gain without feedback)
$β$ = Feedback factor (fraction of output fed back)

Feedback Topologies (4 basic types) :

Topology	Sampled Quantity	Feedback Quantity	Effect on Input Impedance	Effect on Output Impedance
Voltage-Series	Voltage	Voltage	Increases	Decreases
Current-Series	Current	Voltage	Increases	Increases
Voltage-Shunt	Voltage	Current	Decreases	Decreases
Current-Shunt	Current	Current	Decreases	Increases

2.2 Negative vs. Positive Feedback

Aspect	Negative Feedback	Positive Feedback
Effect on Gain	$1 + A β > 1$ , gain decreases	$1 - A β < 1$ , gain increases
Phase Condition	$∠ (A β) = 18 0^{\circ}$ (inverting)	$∠ (A β) = 0^{\circ}$ (non-inverting)
Stability	Stabilizes the amplifier	Destabilizes; leads to oscillation
Distortion	Reduces non-linear distortion	Increases distortion
Bandwidth	Increases bandwidth	Decreases bandwidth
Input/Output Impedance	Can be adjusted by topology	Opposite effect of negative feedback

2.3 Effects of Negative Feedback

Parameter	Effect of Negative Feedback	Formula (for Voltage-Series)
Gain	Decreases	$A_{f} = A / (1 + A β)$
Gain Stability	Improves	$d A_{f} / A_{f} = (1/ (1 + A β)) \cdot d A / A$
Bandwidth	Increases	$B W_{f} = B W (1 + A β)$
Non-linear Distortion	Reduces	$D_{f} = D / (1 + A β)$
Input Impedance	Increases (series), Decreases (shunt)	$Z_{i f} = Z_{i} (1 + A β)$ (series)
Output Impedance	Decreases (voltage), Increases (current)	$Z_{o f} = Z_{o} / (1 + A β)$ (voltage)

2.4 Stability of Feedback Amplifiers

An amplifier with negative feedback can become unstable (oscillate) if the phase shift around the feedback loop reaches 180° while the loop gain is still greater than unity .

Nyquist Stability Criterion: A feedback system is stable if the Nyquist plot of $A β$ does not encircle the point $- 1 + j 0$ .

Bode Stability Criterion (simplified):

Gain Margin: The amount of gain increase (in dB) required to make the system unstable (at the frequency where phase = -180°).
Phase Margin: The amount of additional phase lag (in degrees) required to make the system unstable (at the frequency where gain = 0 dB).

Rule of thumb: A phase margin of at least 45° is required for stable operation.

Part 3: Transistor Amplifier Configurations

3.1 Bipolar Junction Transistor (BJT) Amplifiers

Configuration	Common Emitter (CE)	Common Collector (CC) / Emitter Follower	Common Base (CB)
Input Impedance	Medium (1-5 kΩ)	High (100-500 kΩ)	Low (10-100 Ω)
Output Impedance	Medium (10-100 kΩ)	Low (10-100 Ω)	High (500 kΩ-1 MΩ)
Voltage Gain	High (up to -500)	≈ 1	High
Current Gain	High (β)	High (β)	≈ 1
Phase Shift	180°	0°	0°
Applications	General-purpose gain stages	Impedance matching (buffer)	High-frequency amplifiers

3.2 Field Effect Transistor (FET) Amplifiers

Configuration	Common Source (CS)	Common Drain (CD) / Source Follower	Common Gate (CG)
Input Impedance	Very high (MΩ)	Very high (MΩ)	Low (50-500 Ω)
Voltage Gain	Moderate (up to -50)	≈ 1	Moderate (≈ 20)
Phase Shift	180°	0°	0°
Applications	High-impedance inputs, gain stages	Impedance transformation	High-frequency, cascode stages

3.3 Differential Amplifiers

The differential amplifier is a fundamental building block of operational amplifiers and many integrated circuits. It amplifies the difference between two input signals while rejecting common-mode signals .

Key Parameters:

Parameter	Formula	Ideal Value
Differential Gain ( $A_{d}$ )	$V_{o u t} / (V_{in 1} - V_{in 2})$	High (10³-10⁵)
Common-Mode Gain ( $A_{c m}$ )	$V_{o u t} / V_{in, c m}$	0
Common-Mode Rejection Ratio (CMRR)	$20 log_{10} (A_{d} / A_{c m})$ dB	∞

Output voltage:

$V_{o u t} = A_{d} (V_{in 1} - V_{in 2}) + A_{c m} (2 V ^{in 1} + V ^{in 2})$

Part 4: Power Amplifiers

4.1 Power Amplifier Fundamentals

Power amplifiers are designed to deliver high power to a load (e.g., loudspeaker, antenna). The key performance metrics are :

Efficiency:

$η = P ^{D C} P ^{o u t} \times 100%$

Power Dissipation: $P_{D} = P_{D C} - P_{o u t}$

4.2 Power Amplifier Classes

Class A

Operation: Output device conducts for entire 360° of input cycle
Biasing: Q-point at center of load line
Maximum Efficiency: 50% (resistive load), 25% (transformer-coupled)
Advantages: Excellent linearity, low distortion
Disadvantages: Very inefficient, high power dissipation

Class B (Push-Pull)

Operation: Two output devices each conduct for 180° (alternating)
Biasing: Q-point at cutoff
Maximum Efficiency: 78.5%
Advantages: Much higher efficiency than Class A
Disadvantages: Crossover distortion at zero-crossing

Class AB

Operation: Compromise between Class A and B; each device conducts for >180° but <360°
Biasing: Q-point slightly above cutoff
Efficiency: 50-70%
Advantages: Reduced crossover distortion, good efficiency
Disadvantages: More complex biasing

Class C

Operation: Device conducts for <180° of input cycle
Biasing: Q-point below cutoff (negative bias)
Efficiency: Up to 90%
Advantages: Highest efficiency among linear classes
Disadvantages: Significant distortion; requires tuned load (RF applications)

Class D (Switching)

Operation: Devices operate as switches (fully on or off)
Modulation: Pulse Width Modulation (PWM)
Efficiency: 90-95%
Advantages: Extremely efficient, compact
Disadvantages: Requires output filter, EMI considerations

4.3 Darlington Pair

The Darlington pair is a compound configuration of two bipolar transistors that provides very high current gain .

$β_{t o t a l} \approx β_{1} \times β_{2}$

Characteristics:

Very high current gain (10³-10⁵)
High input impedance
Low output impedance
Base-emitter voltage is twice that of a single transistor ( $V_{BE (t o t a l)} \approx 1.2 - 1.4 V$ ).

Part 5: Operational Amplifiers (Op-Amps)

5.1 Ideal vs. Real Op-Amp

Parameter	Ideal Op-Amp	Real Op-Amp (e.g., 741)
Open-Loop Gain (A)	∞	10⁵ – 10⁶ (100-120 dB)
Input Impedance	∞	1-10 MΩ (bipolar), >10¹² Ω (FET)
Output Impedance	0	50-200 Ω
Bandwidth	∞	0.5-1 MHz (741), higher for modern
Input Bias Current	0	50-500 nA (bipolar), pA (FET)
Input Offset Voltage	0	1-5 mV
CMRR	∞	80-100 dB

5.2 Basic Op-Amp Configurations

Inverting Amplifier :

$V_{o u t} = - R ^{in} R ^{f} V_{in}$ $Z_{in} = R_{in}$

Non-inverting Amplifier :

$V_{o u t} = (1 + R ^{in} R ^{f}) V_{in}$ $Z_{in} \to \infty (ideal)$

Voltage Follower (Buffer) :

$V_{o u t} = V_{in}$

Used for impedance transformation (high input, low output).

Summing Amplifier:

$V_{o u t} = - (R ^{1} R ^{f} V_{1} + R ^{2} R ^{f} V_{2} + \dots + R ^{n} R ^{f} V_{n})$

Differential Amplifier:

$V_{o u t} = R ^{1} R ^{2} (V_{2} - V_{1}) (when R_{2} / R_{1} = R_{4} / R_{3})$

Part 6: Oscillators

6.1 Principles of Oscillation

An oscillator is a circuit that produces a repetitive, periodic waveform (sinusoidal, square, triangular, or sawtooth) without any external input signal. It converts DC power from the supply into AC power at the desired frequency .

6.2 Barkhausen Criterion

For sustained oscillations (steady-state), the following two conditions must be satisfied :

Magnitude Condition: The loop gain must be exactly unity.

$∣ A β ∣ = 1$
Phase Condition: The total phase shift around the loop must be 0° (or 360°).

$∠ (A β) = 0^{\circ} (or 36 0^{\circ})$

Start-up Condition: To initiate oscillations, the loop gain must be slightly greater than unity ( $∣ A β ∣ > 1$ ).

6.3 Frequency Stability

The stability of an oscillator refers to its ability to maintain a constant frequency despite variations in temperature, supply voltage, and component aging. Key factors affecting stability include :

Temperature coefficient of components (L, C, R)
Transistor parasitic capacitances
Power supply variations
Loading effects

Stability measure: $Δ T Δ f$ (Hz/°C) or parts per million (ppm) drift.

6.4 Types of Oscillators

Oscillators can be broadly classified by the frequency-determining network and the type of output waveform.

6.4.1 Sinusoidal Oscillators

RC Oscillators (for audio frequencies, 10 Hz – 1 MHz) :

Type	Frequency-Determining Network	Frequency Equation	Characteristics
Wien Bridge	RC series-parallel network	$f = 2 π RC 1$	Low distortion, amplitude stabilization by thermistor/JFET
Phase-Shift	Three cascaded RC sections	$f = 2 π RC 6 1$	Simple, high distortion, fixed amplitude

LC Oscillators (for radio frequencies, 100 kHz – 100s MHz) :

Type	Configuration	Frequency Equation	Advantages
Hartley	Tapped inductor (or two inductors)	$f = 2 π L ^{e q} C 1$	Single tuning capacitor, easy to tune
Colpitts	Capacitive voltage divider (two capacitors)	$f = 2 π L C ^{e q} 1$	Better frequency stability than Hartley
Clapp	Colpitts with additional series C	$f = 2 π L C ^{e q} 1$	Improved frequency stability

Where $L_{e q} = L_{1} + L_{2} + 2 M$ (Hartley) and $1/ C_{e q} = 1/ C_{1} + 1/ C_{2}$ (Colpitts).

Crystal Oscillators (for high stability, kHz – 100s MHz) :

Uses quartz crystal as resonant element (piezoelectric effect)
Very high Q (10⁴-10⁶) → excellent frequency stability
Frequency stability: 10⁻⁶ to 10⁻¹⁰ (ppm range)
Equivalent circuit: Series LCR (very high L) in parallel with package capacitance $C_{0}$
Operates in series or parallel resonant mode

6.5 Relaxation Oscillators (Non-sinusoidal)

Relaxation oscillators generate non-sinusoidal waveforms (square, triangular, sawtooth) using the charging and discharging of a capacitor .

The 555 Timer IC :

The 555 timer is a versatile integrated circuit for generating accurate timing pulses.

Block Diagram Components:

Three 5kΩ resistors (voltage divider)
Two comparators (upper and lower)
RS flip-flop
Discharge transistor (open collector)

555 as Astable Multivibrator (Free-running oscillator) :

Parameter	Formula
Charge Time (High)	$T_{hi g h} = 0.693 (R_{1} + R_{2}) C$
Discharge Time (Low)	$T_{l o w} = 0.693 (R_{2}) C$
Frequency	$f = ( R ^{1} + 2 R ^{2} ) C 1.44$
Duty Cycle	$D = R ^{1} + 2 R ^{2} R ^{1} + R ^{2}$

555 as Monostable Multivibrator (One-shot) :

Parameter	Formula
Pulse Width	$T = 1.1 RC$

6.6 Multivibrators

Multivibrators are two-state switching circuits. They are essentially relaxation oscillators .

Type	Number of Stable States	Trigger Requirement	Applications
Astable	0	None (free-running)	Clock generators, flashers
Monostable	1	External trigger pulse	Timers, pulse delay circuits
Bistable	2	External trigger pulse	Flip-flops, memory elements, counters

Schmitt Trigger: A comparator with hysteresis (positive feedback). Converts a slowly varying input into a clean square wave. Used for noise immunity and waveform shaping .

Part 7: Phase-Locked Loops (PLLs)

7.1 PLL Fundamentals

A Phase-Locked Loop (PLL) is a feedback control system that synchronizes its output signal with a reference input signal in both frequency and phase .

7.2 Basic PLL Architecture

Reference ──► Phase Detector ──► Loop Filter ──► VCO ──► Output
   │               ▲                            │
   └───────────────┴────────────────────────────┘

7.3 PLL Components

Component	Function
Phase Detector (PD)	Compares phase of reference and feedback signals; produces error voltage proportional to phase difference
Loop Filter (LPF)	Removes high-frequency components; determines PLL dynamics (capture range, lock time)
Voltage-Controlled Oscillator (VCO)	Generates output frequency proportional to input control voltage
Frequency Divider	Divides VCO output for frequency synthesis applications

7.4 PLL Parameters

Parameter	Description
Lock Range	Frequency range over which PLL can maintain lock once acquired
Capture Range	Frequency range over which PLL can acquire lock from an unlocked state
Lock Time	Time required for PLL to lock after a frequency step
Phase Noise	Short-term frequency fluctuations; critical in communication systems

7.5 PLL Applications

Frequency Synthesis: Generating multiple frequencies from a single reference (frequency synthesizers)
FM Demodulation: Recovering modulating signal from FM carrier
Clock Recovery: Extracting clock from data stream (CDR circuits)
Frequency Multiplication/Division: Using dividers in feedback path
Motor Speed Control: Locking motor speed to reference frequency

Part 8: Key Formulas Summary

Concept	Formula
Closed-Loop Gain (Feedback)	$A_{f} = A / (1 + A β)$
Gain Desensitivity	$d A_{f} / A_{f} = (1/ (1 + A β)) \cdot d A / A$
Bandwidth Extension	$B W_{f} = B W (1 + A β)$
Distortion Reduction	$D_{f} = D / (1 + A β)$
Input Impedance (Series Feedback)	$Z_{i f} = Z_{i} (1 + A β)$
Input Impedance (Shunt Feedback)	$Z_{i f} = Z_{i} / (1 + A β)$
Output Impedance (Voltage Feedback)	$Z_{o f} = Z_{o} / (1 + A β)$
Class A Max Efficiency	$η_{ma x} = 25%$ (resistive), 50% (transformer)
Class B Max Efficiency	$η_{ma x} = π /4 \approx 78.5%$
Wien Bridge Oscillator Frequency	$f = 1/ (2 π RC)$
Phase-Shift Oscillator Frequency	$f = 1/ (2 π RC 6)$
Hartley/Colpitts Oscillator Frequency	$f = 1/ (2 π L C)$
555 Astable Frequency	$f = 1.44/ [(R_{1} + 2 R_{2}) C]$
555 Monostable Pulse Width	$T = 1.1 RC$

Part 9: Study Tips for TE-259

Master the Feedback Concept: The feedback equation $A_{f} = A / (1 + A β)$ is the single most important equation in this course. Understand its derivation and application to all four topologies.
Learn to Identify Amplifier Classes: Be able to recognize Class A, B, AB, and C from biasing conditions and conduction angles. Know their efficiency vs. linearity trade-offs.
Understand the Barkhausen Criterion: The two conditions (magnitude = 1, phase = 0°) are essential for oscillator analysis. Practice deriving the frequency of oscillation and start-up conditions for Wien bridge, Hartley, and Colpitts oscillators.
Practice Amplifier Calculations: Work through DC biasing, AC gain, input/output impedance, and frequency response problems for CE, CC, CB, CS, CD, and CG configurations.
Know the 555 Timer: The 555 is a classic example of a relaxation oscillator. Memorize the astable frequency formula and monostable pulse width formula.
Connect to Other Courses: TE-259 builds on basic electronics (diodes, transistors) and prepares you for advanced RF design, communication systems, and power electronics.
Use Simulation Tools: Tools like SPICE, ADS, or MWO help visualize amplifier frequency response and oscillator start-up behavior. The Johns Hopkins course specifically uses ADS or MWO for simulations .
Study Stability: Understand gain margin, phase margin, and the Nyquist criterion. These concepts are critical for designing stable feedback amplifiers and oscillators .

Part 10: Recommended Textbooks and Resources

Resource	Focus
Microwave and RF Design: Amplifiers and Oscillators – Michael Steer	RF/microwave design
Lecture Notes in Analogue Electronics – Vančo Litovski	Small-signal amplification and linear oscillators
The Art of Electronics – Horowitz & Hill	Practical circuit design
How Circuits Work: Amplifiers, Filters, Audio and Control Electronics – Stanislaw Raczynski	Accessible introduction
Course Syllabi: Johns Hopkins University , Kurukshetra University , University of West Macedonia	Course structure and topic coverage

TE-351: Antennas and Wave Propagation

Here are detailed study notes for TE-351: Antennas and Wave Propagation, written from an Electrical/Telecommunication Engineering perspective. These notes cover the fundamental principles of antennas—radiation mechanisms, antenna parameters, antenna types, arrays, and wave propagation phenomena. The emphasis is on understanding how antennas radiate and receive electromagnetic waves and how radio waves propagate through different media.

1. Introduction to Antennas

1.1. What is an Antenna?

An antenna is a transducer that converts guided electromagnetic waves (transmission line) into free-space electromagnetic waves (radiation) and vice versa. It serves as the interface between a transmitter or receiver and the surrounding space.

The Core Question: How do we design and analyze structures that efficiently radiate or receive electromagnetic energy for communication, radar, and other applications?

1.2. Basic Antenna Functions

Function	Description
Transmitting	Converts guided waves to radiated waves
Receiving	Converts incident waves to guided waves
Directivity	Concentrates energy in desired directions
Matching	Provides impedance match to transmission line
Polarization	Determines orientation of electric field

1.3. Historical Development

Year	Development	Contributor
1887	First electromagnetic waves	Hertz
1895	Wireless telegraphy	Marconi
1900s	Yagi-Uda antenna	Yagi, Uda
1930s	Horn antenna	Various
1940s	Parabolic reflector	WWII radar
1950s	Phased arrays	Various
1970s	Microstrip antennas	Munson
1990s-present	MIMO, smart antennas	Modern

1.4. Electromagnetic Spectrum for Antennas

Band	Frequency	Wavelength	Applications
VLF	3-30 kHz	100-10 km	Submarine communication
LF	30-300 kHz	10-1 km	Navigation
MF	300 kHz-3 MHz	1 km-100 m	AM radio
HF	3-30 MHz	100-10 m	Shortwave, amateur radio
VHF	30-300 MHz	10-1 m	FM radio, TV
UHF	300 MHz-3 GHz	1 m-10 cm	Mobile phones, TV
SHF	3-30 GHz	10-1 cm	Satellite, radar, Wi-Fi
EHF	30-300 GHz	10-1 mm	Point-to-point, 5G
THz	0.3-3 THz	1-0.1 mm	Imaging, sensing

2. Antenna Fundamentals

2.1. Radiation Mechanism

Radiation from a current element (Hertzian dipole):

A time-varying current produces a time-varying magnetic field, which in turn produces a time-varying electric field, creating a self-sustaining electromagnetic wave.

For a small dipole of length dl carrying current I:

Near Field (Fresnel region, r < λ/2π):

Fields are predominantly reactive (stored energy)
$E \propto 1/ r^{3}$ , $H \propto 1/ r^{2}$

Far Field (Fraunhofer region, r > 2D²/λ):

Fields are purely radiative
$E \propto 1/ r$ , $H \propto 1/ r$
$E / H = η = 120 π \approx 377Ω$

2.2. Antenna Regions

┌─────────────────────────────────────────────────────────────────┐
│                     Antenna Regions                             │
│                                                                 │
│  ┌──────────┐    ┌──────────────┐    ┌──────────────────────┐   │
│  │ Reactive │    │   Fresnel    │    │      Fraunhofer      │   │
│  │   Near   │    │   (Near)     │    │      (Far Field)     │   │
│  │   Field  │    │   Field      │    │                      │   │
│  │          │    │              │    │                      │   │
│  │  r < λ   │    │  λ < r < 2D²/λ│   │    r > 2D²/λ         │   │
│  └──────────┘    └──────────────┘    └──────────────────────┘   │
│                                                                 │
│  D = largest antenna dimension                                 │
└─────────────────────────────────────────────────────────────────┘

Region	Distance	Field Characteristics
Reactive Near Field	r < λ	Reactive fields dominate
Radiative Near Field (Fresnel)	λ < r < 2D²/λ	Angular distribution depends on distance
Far Field (Fraunhofer)	r > 2D²/λ	Angular distribution independent of distance

2.3. Radiation Pattern

The radiation pattern is the spatial distribution of radiated energy from an antenna.

Types of Radiation Patterns:

Type	Description
Isotropic	Radiates equally in all directions (theoretical)
Directional	Radiates preferentially in certain directions
Omnidirectional	Radiates uniformly in one plane (e.g., horizontal)

Pattern Lobes:

                    ┌─────────────────────────────┐
                    │        Main Lobe            │
                    │         (Beam)              │
                    │           ▲                 │
                    │          / \                │
                    │         /   \               │
                    │        /     \              │
                    │       /       \             │
                    │      /         \            │
                    │     /           \           │
                    └────┴─────────────┴───────→ θ
                   Side    Side       Back
                   Lobe    Lobe       Lobe

Lobe	Description
Main Lobe	Direction of maximum radiation
Side Lobes	Radiation in undesired directions
Back Lobe	Radiation opposite to main lobe
Nulls	Directions of zero radiation

2.4. Antenna Parameters

Beamwidth:

Half-Power Beamwidth (HPBW): Angular width between half-power points (-3 dB points)
First Null Beamwidth (FNBW): Angular width between first nulls

Directivity (D):
The ratio of radiation intensity in a given direction to the average radiation intensity.

$D = U ^{avg} U ^{max} = P ^{rad} 4 π U ^{max}$

For an isotropic antenna: $D = 1$ (0 dBi)

Approximation for narrow beam antenna:

$D \approx θ ^{H P} ϕ ^{H P} 4 π (in radians)$

Gain (G):
The ratio of radiation intensity in a given direction to the radiation intensity of an isotropic antenna with the same input power.

$G = ηD$

Where $η$ = radiation efficiency

Gain in dBi: $G_{dBi} = 10 log_{10} G$

Antenna Efficiency:

$η = P ^{in} P ^{rad} = R ^{rad} + R ^{loss} R ^{rad}$

2.5. Effective Isotropic Radiated Power (EIRP)

$EIRP = P_{in} G$

EIRP is the power that an isotropic antenna would need to radiate to produce the same field strength.

2.6. Radiation Resistance

The equivalent resistance that dissipates power equal to the radiated power.

$P_{rad} = 21 I_{02} R_{rad}$

For a short dipole (length L << λ):

$R_{rad} = 80 π^{2} (λ L)^{2} \approx 790 (λ L)^{2} Ω$

For a half-wave dipole (L = λ/2):

$R_{rad} \approx 73Ω$

2.7. Antenna Impedance

$Z_{in} = R_{in} + j X_{in} = (R_{rad} + R_{loss}) + j X_{in}$

Resonance occurs when $X_{in} = 0$ (purely resistive)

2.8. Bandwidth

$Bandwidth = f ^{c} f ^{max} - f ^{min} \times 100%$

Types:

Impedance bandwidth: Frequency range where VSWR < 2
Pattern bandwidth: Frequency range where pattern characteristics are maintained

2.9. Polarization

Polarization is the orientation of the electric field vector as a function of time.

Type	Description	Applications
Linear	E-field oscillates along a line	Most common
Circular	E-field rotates in a circle	Satellite, GPS
Elliptical	E-field traces an ellipse	General case

Polarization Loss Factor (PLF):

$PLF=∣ρ^t⋅ρ^r∣2=cos⁡2θp$

Where $θ_{p}$ is the angle between polarizations.

Circular Polarization:

Right-Hand Circular Polarization (RHCP): Clockwise when approaching
Left-Hand Circular Polarization (LHCP): Counterclockwise when approaching

2.10. Reciprocity Theorem

An antenna’s transmitting and receiving characteristics are identical:

Same radiation pattern
Same impedance
Same polarization
Same gain

3. Basic Antenna Types

3.1. Hertzian Dipole (Infinitesimal Dipole)

Length: L << λ

Current distribution: Uniform

Radiation pattern:

$E_{θ} = 4 π r I ^{0} L sin θ \cdot λ e ^{- jk r} \cdot j η k$

Power pattern:

$U (θ) = U_{max} sin^{2} θ$

HPBW: 90°
Directivity: D = 1.5 (1.76 dBi)
Radiation resistance: $R_{rad} = 80 π^{2} (L / λ)^{2}$

3.2. Short Dipole

Length: L < λ/10

Current distribution: Triangular (zero at ends, maximum at center)

Radiation pattern: Same as Hertzian dipole (sin²θ)
Directivity: D = 1.5 (1.76 dBi)
Radiation resistance: $R_{rad} = 20 π^{2} (L / λ)^{2}$

3.3. Half-Wave Dipole (λ/2 Dipole)

Length: L = λ/2

Current distribution: Sinusoidal (maximum at center, zero at ends)

Radiation pattern:

$F (θ) = sin θ cos ( 2 π cos θ )$

HPBW: ≈ 78°
Directivity: D = 1.64 (2.15 dBi)
Gain: G ≈ 2.15 dBi (typical)
Radiation resistance: $R_{rad} \approx 73Ω$
Input impedance: $Z_{in} \approx 73 + j 42.5Ω$ (slightly inductive)

3.4. Folded Dipole

Structure: Two parallel dipoles connected at ends

Characteristics:

Input impedance ≈ 292 Ω (4× half-wave dipole)
Wider bandwidth than simple dipole
Commonly used in TV antennas, Yagi-Uda arrays

3.5. Monopole (Quarter-Wave Antenna)

Structure: λ/4 vertical element over ground plane

Current distribution: Sinusoidal (maximum at base, zero at top)

Radiation pattern: Omnidirectional in horizontal plane

Directivity: D = 3.28 (5.15 dBi) (twice dipole)
Input impedance: $Z_{in} \approx 36.5Ω$ (half of dipole)
Gain: G ≈ 5.15 dBi (with perfect ground plane)

Ground plane requirements:

Diameter ≥ λ/2
Radial wires for portable antennas

3.6. Loop Antennas

Small Loop (Circumference << λ):

Parameter	Value
Radiation pattern	sin²θ (same as dipole)
Directivity	1.5 (1.76 dBi)
Radiation resistance	$R_{rad} \approx 20 π^{2} (C / λ)^{4}$ (very small)
Applications	Direction finding, AM radio receivers

Large Loop (Circumference ≈ λ):

Parameter	Value
Radiation pattern	Maximum perpendicular to plane
Directivity	≈ 1.5 (1.76 dBi)
Applications	HF communications

3.7. Yagi-Uda Antenna

Structure:

Reflector (slightly longer than λ/2)
    ↓
Driven element (λ/2 dipole)
    ↓
Directors (slightly shorter than λ/2)
    ↓
    ≈ 0.1-0.25λ spacing

Characteristics:

Parameter	Value
Gain	5-15 dBi
Front-to-back ratio	15-30 dB
Bandwidth	5-10%
Applications	TV reception, amateur radio

Gain approximation:

$G \approx 10 log_{10} (1.2 \times N) dBi$

Where N = number of elements

3.8. Horn Antenna

Types:

Pyramidal horn (rectangular)
Conical horn (circular)
Sectoral horn (flared in one plane)

Characteristics:

Parameter	Value
Gain	10-25 dBi
Bandwidth	Very wide (octaves)
Directivity	High
Applications	Feeds for reflectors, measurements

Gain approximation:

$G = λ ^{2} 4 π A ^{e} \approx λ ^{2} 4 π A ^{p} η$

3.9. Parabolic Reflector Antenna

Structure: Parabolic dish with feed at focal point

Characteristics:

Parameter	Value
Gain	30-60 dBi
Beamwidth	$θ_{H P} \approx 70 D λ$ (degrees)
Directivity	$D = (λ π D)^{2} η$
Applications	Satellite, radar, radio astronomy

Beamwidth:

$θ_{H P} \approx 7 0^{\circ} D λ$

Gain:

$G = η (λ π D)^{2}$

Where η = aperture efficiency (typically 0.5-0.7)

3.10. Microstrip (Patch) Antenna

Structure: Metallic patch on dielectric substrate over ground plane

Characteristics:

Parameter	Value
Gain	5-9 dBi
Bandwidth	1-5%
Size	≈ λ/2 × λ/2
Applications	Mobile phones, GPS, WLAN

Patch dimensions:

$L \approx 2 f ^{r} ε ^{r} c, W \approx 2 f ^{r} 2 ε ^{r} + 1 c$

3.11. Helical Antenna

Modes:

Normal mode: Radiation broadside (small helix)
Axial mode: Radiation end-fire (circumference ≈ λ)

Axial mode characteristics:

Parameter	Value
Gain	10-15 dBi
Bandwidth	Wide
Polarization	Circular
Applications	Satellite communications

4. Antenna Arrays

4.1. Array Fundamentals

An antenna array is a set of multiple antennas arranged to achieve a desired radiation pattern.

Array Factor (AF): The radiation pattern of the array assuming isotropic elements.

$AF = n = 1 \sum N I_{n} e^{j (n - 1) (k d c o s θ + β)}$

Where:

$I_{n}$ = current amplitude of element n
$k = 2 π / λ$ = wave number
$d$ = spacing between elements
$θ$ = angle from array axis
$β$ = phase shift between elements

4.2. Uniform Linear Array

All elements have equal amplitude, progressive phase shift.

Array Factor:

$AF = sin ( ψ /2 ) sin ( N ψ /2 )$

Where $ψ = k d cos θ + β$

Main beam direction:

$θ_{max} = cos^{-1} (- k d β)$

Nulls occur when:

$2 N ψ = mπ, m = 1, 2, \dots, m \neq = N, 2 N, \dots$

Half-Power Beamwidth:

$θ_{H P} \approx N d cos θ ^{0} 0.886 λ (in radians)$

4.3. Broadside Array (β = 0)

Main beam: Perpendicular to array axis (θ = 90°)

Array Factor:

$AF = sin ( k d cos θ /2 ) sin ( N k d cos θ /2 )$

Condition to avoid grating lobes:

$d < λ$

4.4. End-Fire Array (β = -kd)

Main beam: Along array axis (θ = 0° or 180°)

Condition to avoid grating lobes:

$d < λ /2$

Hansen-Woodyard condition for increased directivity:

$β = - (k d + N π)$

4.5. Phased Array

An array where beam direction is controlled electronically by varying the phase shift β.

Beam scanning:

$θ_{0} = cos^{-1} (- k d β)$

Advantages:

Fast beam scanning (no moving parts)
Multiple beams possible
Adaptive beamforming

4.6. Binomial Array

Array with binomial amplitude distribution (no side lobes).

Amplitude coefficients (Pascal’s triangle):

N=2: 1, 1
N=3: 1, 2, 1
N=4: 1, 3, 3, 1
N=5: 1, 4, 6, 4, 1

Disadvantage: Lower directivity than uniform array

4.7. Dolph-Chebyshev Array

Optimal array with minimum beamwidth for a given side lobe level.

Characteristics:

Equal side lobes
Minimum beamwidth for given SLL
Most efficient array design

5. Antenna Measurements

5.1. Key Measurements

Measurement	Description
Radiation pattern	Angular distribution of radiated energy
Gain	Power gain relative to isotropic
Impedance	Input impedance vs. frequency
Polarization	Orientation of electric field
Bandwidth	Frequency range of operation

5.2. Measurement Methods

Directivity measurement:

Pattern integration method
Comparison method (known gain standard)

Gain measurement (two-antenna method):

$G = λ 4 π r P ^{t} P ^{r}$

5.3. Anechoic Chamber

A shielded room with absorbing material to simulate free-space conditions.

Absorbers:

Pyramidal foam (carbon-impregnated)
Ferrite tiles

6. Wave Propagation

6.1. Fundamental Propagation Mechanisms

Mechanism	Description
Reflection	Wave bounces off surfaces (ground, buildings)
Refraction	Wave bends due to changing medium (atmosphere)
Diffraction	Wave bends around obstacles
Scattering	Wave scatters from rough surfaces
Absorption	Energy absorbed by medium

6.2. Free Space Propagation

Friis Transmission Equation:

$P_{r} = P_{t} G_{t} G_{r} (4 π r λ)^{2}$

Path Loss (Free Space):

$PL = (λ 4 π r)^{2}$

In dB:

$PL_{dB} = 20 log_{10} (λ 4 π r) = 32.4 + 20 log_{10} (r_{km}) + 20 log_{10} (f_{MHz})$

Field Strength (rms) from isotropic radiator:

$E = r 30 P ^{t} G ^{t} (V/m)$

6.3. Propagation Models

Two-Ray (Ground Reflection) Model:

$P_{r} = P_{t} G_{t} G_{r} (r ^{2} h ^{t} h ^{r})^{2}$

Path Loss:

$PL \propto 1/ r^{4} (far field)$

Breakpoint distance:

$r_{b} = λ 4 π h ^{t} h ^{r}$

6.4. Atmospheric Effects

Atmospheric Refraction:

Bends waves downward (k-factor)
Effective Earth radius: $R_{e} = k R$ (k ≈ 4/3 typical)

Super-refraction (ducting):

Waves trapped in atmospheric duct
Extended propagation range

Sub-refraction:

Waves bend upward
Reduced range

6.5. Tropospheric Propagation

Mode	Frequency	Range	Characteristics
Line of Sight (LOS)	> 30 MHz	Up to horizon	Most reliable
Tropospheric scatter	100 MHz-10 GHz	100-500 km	Low signal level
Ducting	> 100 MHz	Very long	Intermittent

Radio Horizon:

$d_{horizon} = 2 h^{t} + 2 h^{r} (miles, h in feet)$ $d_{horizon} = 4.12 (h^{t} + h^{r}) (km, h in meters)$

6.6. Ionospheric Propagation

Ionosphere Layers:

Layer	Height (km)	Behavior
D	50-90	Absorbs daytime, disappears at night
E	90-120	Supports some propagation
F1	150-200	Combines with F2 at night
F2	200-500	Main propagation layer

Critical Frequency (f_c): Highest frequency reflected at vertical incidence

$f_{c} = 9 N^{max} (Hz)$

Maximum Usable Frequency (MUF):

$MUF = f_{c} sec θ_{i}$

Optimum Working Frequency (OWF):

$OWF = 0.85 \times MUF$

Skip Distance: Minimum distance for ionospheric return

6.7. Ground Wave Propagation

Component	Description
Surface wave	Follows Earth’s curvature
Space wave	Direct + reflected wave
Ground wave	Surface wave + space wave

Frequency range: < 2 MHz
Polarization: Vertical (horizontal is attenuated)
Applications: AM radio, maritime communications

6.8. Space Wave Propagation

Components:

Direct wave (LOS)
Reflected wave (ground)
Diffracted wave (over obstacles)

Applications: FM radio, TV, cellular, microwave

6.9. Fading

Type	Description	Mitigation
Flat fading	All frequencies affected equally	Diversity
Frequency selective	Different frequencies affected differently	Equalization
Slow fading	Changes slowly (shadowing)	Power control
Fast fading	Changes rapidly (multipath)	Diversity, interleaving

Multipath Fading Statistics:

Rayleigh fading: No LOS component
Rician fading: Dominant LOS component

7. Key Equations Reference Sheet

Equation	Description
$G = ηD$	Antenna gain
$D = 4 π U_{max} / P_{rad}$	Directivity
$R_{rad} = 80 π^{2} (L / λ)^{2}$	Short dipole radiation resistance
$θ_{H P} \approx 70 λ / D$	Parabolic reflector beamwidth
$G = η (π D / λ)^{2}$	Parabolic reflector gain
$AF = s i n ( ψ /2 ) s i n ( N ψ /2 )$	Array factor
$P_{r} = P_{t} G_{t} G_{r} (λ /4 π r)^{2}$	Friis transmission equation
$PL_{dB} = 32.4 + 20 log_{10} r_{km} + 20 log_{10} f_{MHz}$	Free space path loss
$d_{horizon} = 4.12 (h^{t} + h^{r})$	Radio horizon (km)
$MUF = f_{c} sec θ_{i}$	Maximum usable frequency

8. Standard Textbooks

Author	Title	Focus
Balanis, C.A.	Antenna Theory: Analysis and Design	Comprehensive
Kraus & Marhefka	Antennas for All Applications	Practical
Stutzman & Thiele	Antenna Theory and Design	Engineering focus
Jordan & Balmain	Electromagnetic Waves and Radiating Systems	Classic

9. Final Study Checklist

Topic	Key Skills
Antenna Parameters	Calculate gain, directivity, beamwidth, efficiency
Basic Antennas	Analyze dipole, monopole, loop, Yagi, patch, reflector
Arrays	Calculate array factor; design broadside and end-fire arrays
Antenna Measurements	Describe pattern, gain, impedance measurements
Free Space Propagation	Apply Friis equation; calculate path loss
Ionospheric Propagation	Explain MUF, skip distance, critical frequency
Tropospheric Propagation	Explain LOS, ducting, scattering, radio horizon
Fading	Distinguish fading types; identify mitigation methods

TE-471: Opto-Electronics – Comprehensive Study Notes

These notes provide a complete framework for Opto-Electronics, covering the fundamental principles of interaction between light and electronic devices. The focus is on understanding the physics of photon generation, transmission, detection, and modulation within semiconductor devices. This field is fundamental to modern technologies such as fiber-optic communication, displays, solid-state lighting, and medical imaging .

Part 1: Fundamentals of Optoelectronics

1.1 What is Optoelectronics?

Optoelectronics is the branch of physics and engineering that deals with devices and systems that source, detect, and control light, typically involving the conversion of electrical energy to optical energy (and vice versa) . It serves as the critical interface between electronics (electrons) and photonics (photons).

The core principle relies on the interaction of light with matter, specifically semiconductors. When a photon strikes a semiconductor, it can be absorbed, generating an electrical signal (photodetection). Conversely, when an electrical current flows through a semiconductor, it can recombine to emit a photon (light emission) .

1.2 The Nature of Light (Wave-Particle Duality)

Understanding light requires embracing its dual nature.

As an Electromagnetic Wave:

Frequency ( $f$ ): Number of oscillations per second (Hz).
Wavelength ( $λ$ ): Distance between successive peaks (m, nm).
Velocity ( $c$ ): $c = f λ$ . In a vacuum, $c = 3 \times 1 0^{8}$ m/s .

The Electromagnetic Spectrum:
Optoelectronics primarily utilizes the visible spectrum (380-750 nm) and the adjacent infrared (IR) and ultraviolet (UV) bands .

Band	Wavelength	Photon Energy (eV)	Typical Applications
Ultraviolet (UV)	10-380 nm	>3.26	Lithography, sterilization
Visible (VIS)	380-750 nm	1.65-3.26	Displays, lighting
Near-Infrared (NIR)	750-1500 nm	0.83-1.65	Fiber optics, remote controls
Mid-Infrared (MIR)	1500-5000 nm	0.25-0.83	Thermal imaging, sensing

As a Particle (Photon):
Light carries energy in discrete packets called photons. The energy of a single photon is proportional to its frequency.

$E = h f = λ h c$

Where:

$E$ = Energy (Joules or electron-volts, eV)
$h$ = Planck’s constant ( $6.626 \times 1 0^{-34}$ J·s)

1.3 Light-Matter Interaction in Semiconductors

The interaction is governed by the bandgap energy ( $E_{g}$ ) of the semiconductor .

Absorption (Photodetection):
If a photon has energy greater than or equal to the bandgap ( $E \geq E_{g}$ ), it can be absorbed, exciting an electron from the valence band to the conduction band. This creates an electron-hole pair (EHP) and generates a photocurrent. The critical wavelength for absorption is:

$λ_{c} (μ m) = E ^{g} ( e V ) 1.24$

Spontaneous Emission (LEDs):
When an electron in the conduction band recombines with a hole in the valence band, the energy difference ( $E_{g}$ ) can be released as a photon (light). In LEDs, this process occurs randomly and spontaneously when the device is forward-biased .

Stimulated Emission (Laser Diodes):
An incoming photon can interact with an excited electron, causing it to recombine and emit a second photon that is identical in phase, wavelength, and direction to the first. This process is the basis for optical amplification and laser operation .

Part 2: Light Emitting Diodes (LEDs)

2.1 Device Physics

An LED is a forward-biased p-n junction that emits light via spontaneous emission . The color (wavelength) of the light is determined by the bandgap energy of the semiconductor material used.

Key Principle:
When forward bias is applied, electrons and holes are injected into the depletion region (or active region). Here, they recombine radiatively, producing photons.

Quantum Efficiency:

Internal Quantum Efficiency (IQE) : The ratio of photons generated inside the semiconductor to the number of charge carriers injected.
Extraction Efficiency: The ratio of photons that escape the device (get out of the semiconductor chip) to the photons generated. This is limited by Total Internal Reflection (TIR) due to the high refractive index of semiconductors.

2.2 Materials and Colors

The choice of semiconductor alloy determines the emission wavelength .

Material System	Wavelength Range	Color	Applications
AlGaAs	620-900 nm	Red to NIR	Indicators, optical mice
AlGaInP	560-650 nm	Green to Red	High-brightness red/orange LEDs
InGaN	450-530 nm	Blue to Green	White LEDs (with phosphor), projectors
GaN	365-405 nm	UV	UV curing, disinfection

White LEDs:
There are two primary methods to create white light:

Phosphor-Converted (pc-LED) : A blue InGaN LED is coated with a yellow phosphor (YAG:Ce). The blue light excites the phosphor to emit yellow light; the mix of blue and yellow appears white.
RGB Mixing: Red, green, and blue LEDs are combined in a single package, mixing to form white light (and any other color).

2.3 LED Characteristics

I-V Curve: Similar to a standard diode with a turn-on voltage ( $V_{F}$ ) corresponding to the bandgap ( $V_{F} \approx E_{g} / q$ ).
L-I Curve (Light-Current): Shows a linear relationship between light output and drive current.
Efficiency Droop: A phenomenon where the efficiency of an InGaN LED decreases at high current densities, a major challenge for high-power lighting.
Lambertian Pattern: Most standard LEDs emit light in a Lambertian pattern, where the intensity is highest on-axis and drops off with the cosine of the viewing angle.

2.4 Modern Variants

OLED (Organic LED) : Uses organic molecules or polymers as the semiconductor material. Enables thin, flexible, and large-area displays .
Micro-LED: Extremely small LEDs ( < 100 µm) used for high-brightness, high-efficiency displays with excellent contrast .
Quantum Dot LED (QLED) : Uses quantum dots as the emissive layer, providing very pure colors .

Part 3: Laser Diodes (Semiconductor Lasers)

3.1 Principles of Lasing

A Laser Diode (LD) is a semiconductor device that emits coherent light via stimulated emission. While an LED is a spontaneous emitter, a laser is an optical oscillator .

Three Requirements for Lasing:

Population Inversion: A non-equilibrium condition where there are more electrons in the conduction band (excited state) than in the valence band (ground state). In LEDs, forward bias creates a minority carrier injection; in laser diodes, it creates a population inversion.
Optical Resonator (Cavity) : The ends of the semiconductor chip are cleaved to form mirrors. This provides optical feedback, forcing photons to bounce back and forth through the gain medium to stimulate more emissions.
Gain > Loss: The optical gain provided by the stimulated emission must exceed all losses (absorption, scattering, mirror transmission).

3.2 Laser Diode Structure

Fabry-Pérot Laser Diode:

Active Layer: The thin semiconductor layer (quantum well) where light is generated.
Cladding Layers: Surround the active layer, providing optical confinement (waveguide) and carrier confinement.
Cleaved Facets: The front and back mirrors. The front facet typically has a lower reflectivity to allow laser light to escape.

Distributed Feedback (DFB) Laser:

Uses a diffraction grating (corrugated structure) built into the laser instead of cleaved facets. This allows the laser to operate on a single, very stable wavelength, which is essential for long-haul fiber optic communication.

3.3 L-I-V Characteristics

Threshold Current ( $I_{t h}$ ) : The current at which lasing begins. Below $I_{t h}$ , the device acts like an inefficient LED. Above $I_{t h}$ , the light output increases dramatically and coherently.
Slope Efficiency: The slope of the L-I curve above threshold.
Spectral Width: Lasers have an extremely narrow spectral width (nm or less), while LEDs have a broad spectrum (tens of nm).

Part 4: Photodetectors

4.1 Principles of Operation

Photodetectors convert incident light into an electrical signal. The fundamental mechanism is the internal photoelectric effect: absorption of photons creates electron-hole pairs, which are then collected as a current .

Key Performance Metrics:

Parameter	Symbol	Definition	Formula
Responsivity	$R$	Output current per unit input optical power.	$R = P ^{o pt} I ^{p h}$ (A/W)
Quantum Efficiency (QE)	$η$	Ratio of collected charge carriers to incident photons.	$η = P ^{o pt} / h ν I ^{p h} / q$
Dark Current	$I_{d a r k}$	Small current that flows even when no light is incident.	–
Noise Equivalent Power (NEP)	NEP	The optical power needed to achieve a SNR of 1.	–

4.2 Types of Photodetectors

PIN Photodiode:

Structure: A layer of intrinsic (undoped) semiconductor is sandwiched between P and N layers.
Operation: The intrinsic region acts as a large depletion region, increasing the volume for light absorption and reducing capacitance, resulting in high speed and efficiency. This is the most common type for fiber optics .

Avalanche Photodiode (APD) :

Structure: Similar to PIN but operated at a high reverse bias voltage near the breakdown point.
Operation: Photogenerated carriers gain enough energy from the strong electric field to ionize other atoms via impact ionization, creating an “avalanche” of carriers and providing internal gain (M = 100-1000).
Advantage: Much higher sensitivity, ideal for long-distance fiber links.
Disadvantage: Requires high-voltage bias and generates more noise.

Phototransistor:

Structure: A bipolar junction transistor (BJT) with a base region exposed to light.
Operation: The photocurrent acts as the base current, which is then amplified by the transistor’s current gain ( $β$ ).
Advantage: High sensitivity, good for slow-speed applications.

Metal-Semiconductor-Metal (MSM) Photodetector:

Structure: Two interdigitated (finger-like) metal contacts on a semiconductor, forming two back-to-back Schottky diodes.
Advantage: Very high speed, easy integration with FET electronics .

Part 5: Solar Cells (Photovoltaic Cells)

5.1 Principle of Operation

A solar cell is essentially a large-area photodiode optimized for energy conversion rather than signal detection. It operates in photovoltaic mode (zero bias) .

Operation:

Photon Absorption: Light creates electron-hole pairs in the semiconductor.
Charge Separation: The built-in electric field of the p-n junction separates the electrons and holes, sending electrons to the N-side and holes to the P-side.
Power Delivery: If an external circuit connects the P and N sides, the accumulated charges will flow as current, delivering electrical power to the load.

5.2 I-V Characteristics

Short-Circuit Current ( $I_{sc}$ ) : The current when the cell is shorted (V=0). Directly proportional to light intensity.
Open-Circuit Voltage ( $V_{oc}$ ) : The voltage when the cell is open (I=0). Depends on the semiconductor’s bandgap.
Maximum Power Point (MPP) : The operating point on the I-V curve where the product of current and voltage ( $P = I \times V$ ) is maximized.
Fill Factor (FF) : A measure of the “squareness” of the I-V curve.

$FF = V ^{oc} \times I ^{sc} P ^{ma x}$

Conversion Efficiency ( $η$ ) : The ratio of electrical power output to optical power input.

$η = P ^{in c i d e n t} V ^{oc} \times I ^{sc} \times FF$

5.3 Technologies and Materials

Generation	Material	Efficiency (Lab)	Features
1st Gen	Crystalline Silicon (c-Si)	25-27%	Dominates the market, rigid, expensive.
2nd Gen	Thin-Film (CdTe, CIGS)	20-23%	Low-cost, flexible, lower efficiency.
3rd Gen	Perovskite	25%+	Extremely high potential, low cost, stability issues.
3rd Gen	Organic/Polymer	15-18%	Flexible, printable, lightweight.
3rd Gen	Quantum Dot	16-18%	Tunable bandgap, solution-processable .

Part 6: Optical Waveguides and Fibers

6.1 Principle of Total Internal Reflection (TIR)

An optical waveguide confines light using the principle of TIR. Light traveling in a high-refractive-index core will be totally reflected at the interface with a low-refractive-index cladding if the angle of incidence is greater than the critical angle ( $θ_{c}$ ) .

$θ_{c} = arcsin (n ^{1} n ^{2})$

Numerical Aperture (NA) :

$N A = n_{0} sin θ_{a} = n^{12} - n^{22}$

The NA defines the light-gathering ability of the fiber. A higher NA collects more light but can lead to higher dispersion.

6.2 Types of Optical Fibers

Type	Core Diameter	Refractive Index Profile	Bandwidth-Distance	Application
Single-Mode (SMF)	8-10 µm	Step-Index	Very High	Long-haul telecom, CATV
Multimode (MMF)	50-62.5 µm	Graded-Index	Moderate	Short distances, LAN, data centers

6.3 Signal Degradation

Attenuation (Loss) : The reduction in optical power as light travels through the fiber, measured in dB/km. Low-loss windows exist at 850 nm, 1310 nm, and 1550 nm.

Chromatic Dispersion: Different wavelengths (colors) of light travel at slightly different speeds, causing a pulse to spread. The zero-dispersion wavelength for standard SMF is approximately 1310 nm.

Part 7: Optical Modulators

7.1 Need for Modulation

To transmit information (data, audio, video) over an optical fiber, the light source (laser or LED) must be modulated. This can be done either by directly modulating the current to the laser (Direct Modulation) or by using an external modulator on a continuous-wave (CW) laser.

7.2 Electro-Optic Modulators

External modulators are essential for high-speed, long-distance communication .

Mach-Zehnder Modulator (MZM) (often made of Lithium Niobate, LiNbO₃):

Principle: Uses the electro-optic effect (Pockels effect), where the refractive index of a material changes in response to an applied voltage.
Operation: A CW laser is split into two paths (arms). An electric signal (data) applied to one arm changes its refractive index, altering the phase of the light traveling through it. When the two arms are recombined, the phase difference causes constructive interference (output = 1) or destructive interference (output = 0). This converts an electrical signal directly into an optical signal.

Electro-Absorption Modulator (EAM) :

Principle: Uses the Quantum-Confined Stark Effect (QCSE) in semiconductor quantum wells. An applied voltage shifts the absorption edge of the material, allowing it to either absorb or transmit light. EAMs are easily integrated with laser diodes on a single chip.

Part 8: Key Formulas Summary

Concept	Formula
Photon Energy	$E = h f = h c / λ$
Wavelength for Bandgap	$λ (μ m) = 1.24/ E_{g} (e V)$
Responsivity	$R = I_{p h} / P_{o pt}$ (A/W)
Quantum Efficiency	$η = R \cdot (h c / q λ)$
Numerical Aperture	$N A = n^{12} - n^{22}$
Solar Cell Fill Factor	$FF = P_{ma x} / (V_{oc} I_{sc})$
Laser Threshold Condition	$g_{t h} = α_{l oss} + 2 L 1 ln (R ^{1} R ^{2} 1)$

Part 9: Study Tips for TE-471

Master the Bandgap: The single most important concept in semiconductor optoelectronics. Everything from the color of an LED to the sensitivity of a photodetector traces back to the bandgap energy.
Distinguish Emission Processes: Clearly differentiate between spontaneous emission (LEDs), stimulated emission (lasers), and absorption (photodetectors) .
Connect to Real-World Applications: When studying a device, always ask “Where is this used?” (e.g., APDs for long-haul telecom, LEDs for lighting, OLEDs for displays).
Practice Power Budget Calculations: Many exam problems involve calculating received optical power for a given fiber link, using attenuation coefficients (dB/km) and connector/splice losses.
Use the Search Results: The course syllabi confirm core topics: fundamental principles, detectors, sources, waveguides, and fiber optics .
Visualize the Physics: Draw band diagrams for a p-n junction under forward bias (LED) and reverse bias (photodiode) to visualize carrier flow and depletion regions.

Part 10: Recommended Textbooks and Resources

Resource	Focus
Optoelectronics and Photonics: Principles and Practices – S.O. Kasap	Comprehensive standard textbook
Fundamentals of Photonics – B.E.A. Saleh & M.C. Teich	In-depth theoretical coverage
Optoelectronics and Photonics Engineering – Partha S. Dutta	System design approach
Semiconductor Optoelectronic Devices – Pallab Bhattacharya	Detailed device physics

These notes provide a comprehensive framework for TE-471: Opto-Electronics. Success requires understanding the light-matter interaction in semiconductors, mastering device physics (LEDs, laser diodes, photodetectors, solar cells), applying waveguide principles, and connecting theory to practical systems (fiber optics, displays, energy harvesting). Opto-electronics is the enabling technology for the internet, advanced manufacturing, renewable energy, and modern medicine.

TE-359 Signals & Systems – Detailed Study Notes

These study notes are designed for undergraduate engineering students taking a course in Signals and Systems. The notes cover the fundamental principles of continuous-time and discrete-time signals, system properties, time-domain analysis, Fourier analysis, Laplace transforms, Z-transforms, and system applications.

1. Introduction to Signals and Systems

1.1 What is a Signal?

Aspect	Detail
Definition	A signal is a function that conveys information about a physical phenomenon, varying with one or more independent variables (usually time).
Examples	Speech (acoustic pressure vs. time), ECG (voltage vs. time), image (brightness vs. position), temperature (temperature vs. time)

1.2 Classification of Signals

Classification	Types	Examples
By nature	Continuous-time (CT): x(t), t ∈ ℝ Discrete-time (DT): x[n], n ∈ ℤ	CT: analog audio, DT: digital samples
By periodicity	Periodic: x(t+T)=x(t) Aperiodic (non-periodic)	Sine wave vs. speech
By symmetry	Even: x(-t)=x(t) Odd: x(-t)=-x(t)	Cosine, sine
By energy/power	Energy signal: 0 < E < ∞ Power signal: 0 < P < ∞	Finite duration, periodic
By determinism	Deterministic: known exactly Random: described by probability	Sinusoid, noise

1.3 Basic Continuous-Time Signals

Signal	Notation	Mathematical Description
Unit step	u(t)	u(t) = 0 for t < 0, = 1 for t ≥ 0
Unit impulse (Dirac delta)	δ(t)	∫δ(t)dt = 1, δ(t)=0 for t≠0
Unit ramp	r(t)	r(t) = t for t ≥ 0, = 0 for t < 0
Rectangular pulse	rect(t/T)	1 for	t	< T/2, 0 elsewhere
Sinc function	sinc(t)	sinc(t) = sin(πt)/(πt)
Exponential	e^{at}	a real or complex
Sinusoidal	cos(ωt), sin(ωt)	ω = 2πf = angular frequency

1.4 Basic Discrete-Time Signals

Signal	Notation	Mathematical Description
Unit step	u[n]	u[n] = 0 for n < 0, = 1 for n ≥ 0
Unit impulse (Kronecker delta)	δ[n]	δ[n] = 1 for n = 0, = 0 for n ≠ 0
Unit ramp	r[n]	r[n] = n for n ≥ 0, = 0 for n < 0
Exponential	a^n	a real or complex
Sinusoidal	cos(Ωn), sin(Ωn)	Ω = digital frequency (rad/sample)

1.5 Signal Operations

Operation	Continuous-Time	Discrete-Time
Time scaling	x(at)	x[kn] (downsampling), x[n/k] (upsampling)
Time shifting	x(t – t₀)	x[n – n₀]
Time reversal	x(-t)	x[-n]
Amplitude scaling	c·x(t)	c·x[n]
Addition	x₁(t) + x₂(t)	x₁[n] + x₂[n]
Multiplication	x₁(t)·x₂(t)	x₁[n]·x₂[n]
Convolution	x(t) * h(t) = ∫x(τ)h(t-τ)dτ	x[n] * h[n] = Σ x[k]h[n-k]

1.6 Energy and Power of Signals

Energy (CT):

E = ∫_{-∞}^{∞} |x(t)|² dt

Energy (DT):

E = Σ_{n=-∞}^{∞} |x[n]|²

Average Power (CT):

P = lim_{T→∞} (1/T) ∫_{-T/2}^{T/2} |x(t)|² dt

Average Power (DT):

P = lim_{N→∞} (1/(2N+1)) Σ_{n=-N}^{N} |x[n]|²

Classification:

Energy signal: 0 < E < ∞, P = 0
Power signal: 0 < P < ∞, E = ∞

2. Systems and Their Properties

2.1 System Definition

Aspect	Detail
Definition	A system is an entity that processes an input signal to produce an output signal: y(t) = T[x(t)]
Representation	Input-output relationship, differential/difference equation, impulse response, transfer function

2.2 System Properties

Property	Definition	Test
Memoryless	Output depends only on current input	y(t) depends only on x(t), not x(t-τ)
Causal	Output depends only on past and present inputs	h(t) = 0 for t < 0
Linear	T[ax₁+bx₂] = aT[x₁] + bT[x₂]	Superposition + homogeneity
Time-invariant	T[x(t-t₀)] = y(t-t₀)	System parameters don’t change with time
Stable (BIBO)	Bounded input → Bounded output	∫	h(t)	dt < ∞ (CT), Σ	h[n]	< ∞ (DT)
Invertible	Input can be recovered from output	System has an inverse

2.3 Linear Time-Invariant (LTI) Systems

Aspect	Detail
Definition	Systems that are both linear and time-invariant
Significance	Most important class of systems in signal processing
Characterization	Impulse response h(t) (CT) or h[n] (DT) completely characterizes the system

2.4 Convolution

Continuous-Time Convolution:

y(t) = x(t) * h(t) = ∫_{-∞}^{∞} x(τ) h(t-τ) dτ

Properties of Convolution:

Commutative: x * h = h * x
Associative: (x * h₁) * h₂ = x * (h₁ * h₂)
Distributive: x * (h₁ + h₂) = x * h₁ + x * h₂
Identity: x * δ = x

Discrete-Time Convolution:

y[n] = x[n] * h[n] = Σ_{k=-∞}^{∞} x[k] h[n-k]

2.5 Convolution with Impulse

Operation	Result
x(t) * δ(t)	x(t)
x(t) * δ(t – t₀)	x(t – t₀)
x(t) * δ'(t)	x'(t)
x[n] * δ[n]	x[n]
x[n] * δ[n – n₀]	x[n – n₀]

2.6 Convolution with Step

Operation	Result
x(t) * u(t)	∫_{-∞}^{t} x(τ) dτ
u(t) * u(t)	r(t) = t·u(t)
u[n] * u[n]	(n+1)·u[n]

3. Fourier Analysis of Continuous-Time Signals

3.1 Fourier Series (Periodic Signals)

Trigonometric Fourier Series:

x(t) = a₀ + Σ_{n=1}^{∞} [a_n cos(nω₀t) + b_n sin(nω₀t)]

where ω₀ = 2π/T (fundamental frequency)

Coefficients:

a₀ = (1/T) ∫_{t₀}^{t₀+T} x(t) dt
a_n = (2/T) ∫_{t₀}^{t₀+T} x(t) cos(nω₀t) dt
b_n = (2/T) ∫_{t₀}^{t₀+T} x(t) sin(nω₀t) dt

Exponential (Complex) Fourier Series:

x(t) = Σ_{n=-∞}^{∞} c_n e^{jnω₀t}
c_n = (1/T) ∫_{t₀}^{t₀+T} x(t) e^{-jnω₀t} dt

Relationships:

c₀ = a₀
c_n = (a_n - jb_n)/2,   n > 0
c_{-n} = (a_n + jb_n)/2

Properties:

If x(t) is even: b_n = 0, c_n real
If x(t) is odd: a_n = 0, c_n imaginary
Parseval’s theorem: (1/T)∫|x(t)|²dt = Σ|c_n|²

3.2 Fourier Transform (Aperiodic Signals)

Definition:

X(ω) = F[x(t)] = ∫_{-∞}^{∞} x(t) e^{-jωt} dt

Inverse Fourier Transform:

x(t) = F^{-1}[X(ω)] = (1/2π) ∫_{-∞}^{∞} X(ω) e^{jωt} dω

3.3 Properties of Fourier Transform

Property	Time Domain	Frequency Domain
Linearity	ax₁(t) + bx₂(t)	aX₁(ω) + bX₂(ω)
Time shifting	x(t – t₀)	e^{-jωt₀}X(ω)
Frequency shifting	e^{jω₀t}x(t)	X(ω – ω₀)
Time scaling	x(at)	(1/	a	) X(ω/a)
Time reversal	x(-t)	X(-ω)
Duality	X(t)	2πx(-ω)
Differentiation	dx(t)/dt	jω X(ω)
Integration	∫_{-∞}^{t} x(τ)dτ	X(ω)/(jω) + πX(0)δ(ω)
Multiplication	x₁(t)x₂(t)	(1/2π)X₁ * X₂
Convolution	x₁(t) * x₂(t)	X₁(ω)X₂(ω)
Parseval	∫	x(t)	²dt	(1/2π)∫	X(ω)	²dω

3.4 Fourier Transforms of Common Signals

Signal	Fourier Transform
δ(t)	1
1	2πδ(ω)
δ(t – t₀)	e^{-jωt₀}
e^{jω₀t}	2πδ(ω – ω₀)
u(t)	πδ(ω) + 1/(jω)
sgn(t)	2/(jω)
rect(t/T)	T sinc(ωT/2)
sinc(Wt)	(π/W) rect(ω/2W)
e^{-at}u(t), a>0	1/(a + jω)
e^{-a	t	}, a>0	2a/(a² + ω²)
e^{-at²}	√(π/a) e^{-ω²/(4a)}
cos(ω₀t)	π[δ(ω-ω₀) + δ(ω+ω₀)]
sin(ω₀t)	jπ[δ(ω+ω₀) – δ(ω-ω₀)]

3.5 Fourier Transform of Periodic Signals

For a periodic signal x(t) with Fourier series coefficients c_n:

X(ω) = 2π Σ_{n=-∞}^{∞} c_n δ(ω - nω₀)

4. Fourier Analysis of Discrete-Time Signals

4.1 Discrete-Time Fourier Transform (DTFT)

Definition:

X(e^{jΩ}) = DTFT[x[n]] = Σ_{n=-∞}^{∞} x[n] e^{-jΩn}

Inverse DTFT:

x[n] = (1/2π) ∫_{-π}^{π} X(e^{jΩ}) e^{jΩn} dΩ

Properties:

Periodic in Ω with period 2π: X(e^{j(Ω+2π)}) = X(e^{jΩ})
Ω = digital frequency (radians per sample)
Relationships: Ω = ωT (ω = analog frequency, T = sampling period)

4.2 Discrete Fourier Transform (DFT)

Definition (N-point DFT):

X[k] = Σ_{n=0}^{N-1} x[n] e^{-j2πkn/N},   k = 0, 1, ..., N-1

Inverse DFT (IDFT):

x[n] = (1/N) Σ_{k=0}^{N-1} X[k] e^{j2πkn/N},   n = 0, 1, ..., N-1

DFT Properties:

Periodicity: X[k+N] = X[k]
Conjugate symmetry for real x[n]: X[N-k] = X*[k]
Parseval: Σ|x[n]|² = (1/N) Σ|X[k]|²

4.3 Fast Fourier Transform (FFT)

Aspect	Detail
Purpose	Efficient algorithm to compute DFT
Complexity	O(N log₂ N) vs. O(N²) for DFT
Radix-2 FFT	Requires N = 2ᵐ
Decimation-in-time	Split into even and odd indices
Decimation-in-frequency	Split into first and second halves

5. Laplace Transform

5.1 Definition

Bilateral Laplace Transform:

X(s) = ∫_{-∞}^{∞} x(t) e^{-st} dt,   s = σ + jω

Unilateral Laplace Transform (for causal signals):

X(s) = ∫_{0}^{∞} x(t) e^{-st} dt

Inverse Laplace Transform:

x(t) = (1/2πj) ∫_{σ-j∞}^{σ+j∞} X(s) e^{st} ds

5.2 Region of Convergence (ROC)

Aspect	Detail
Definition	Set of s for which the Laplace transform converges
ROC for causal signals	Re(s) > σ₀ (right-half plane)
ROC for anti-causal signals	Re(s) < σ₀ (left-half plane)
ROC for two-sided signals	σ₁ < Re(s) < σ₂ (strip)

5.3 Properties of Laplace Transform

Property	Time Domain	s-Domain
Linearity	ax₁(t)+bx₂(t)	aX₁(s)+bX₂(s)
Time shifting	x(t-t₀)u(t-t₀)	e^{-st₀}X(s)
Frequency shifting	e^{s₀t}x(t)	X(s-s₀)
Time scaling	x(at)	(1/	a	)X(s/a)
Differentiation	dx(t)/dt	sX(s)-x(0⁻)
Integration	∫₀ᵗ x(τ)dτ	X(s)/s
Convolution	x₁(t)*x₂(t)	X₁(s)X₂(s)
Initial value	x(0⁺)=lim_{s→∞} sX(s)	–
Final value	lim_{t→∞}x(t)=lim_{s→0} sX(s)	(if stable)

5.4 Laplace Transforms of Common Signals

Signal	Laplace Transform	ROC
δ(t)	1	All s
u(t)	1/s	Re(s) > 0
r(t) = t·u(t)	1/s²	Re(s) > 0
tⁿu(t)	n!/sⁿ⁺¹	Re(s) > 0
e^{-at}u(t)	1/(s+a)	Re(s) > -a
t e^{-at}u(t)	1/(s+a)²	Re(s) > -a
sin(ωt)u(t)	ω/(s²+ω²)	Re(s) > 0
cos(ωt)u(t)	s/(s²+ω²)	Re(s) > 0
e^{-at}sin(ωt)u(t)	ω/[(s+a)²+ω²]	Re(s) > -a
e^{-at}cos(ωt)u(t)	(s+a)/[(s+a)²+ω²]	Re(s) > -a

5.5 Solving Differential Equations using Laplace Transform

Steps:

Take Laplace transform of both sides
Use initial conditions
Solve for Y(s)
Take inverse Laplace transform

6. Z-Transform

6.1 Definition

Bilateral Z-Transform:

X(z) = Σ_{n=-∞}^{∞} x[n] z^{-n},   z = re^{jΩ}

Unilateral Z-Transform (for causal sequences):

X(z) = Σ_{n=0}^{∞} x[n] z^{-n}

Inverse Z-Transform:

x[n] = (1/2πj) ∮_C X(z) z^{n-1} dz

6.2 Region of Convergence (ROC)

Aspect	Detail
ROC for causal sequences		z	> r₀ (outside circle)
ROC for anti-causal sequences		z	< r₀ (inside circle)
ROC for two-sided sequences	r₁ <	z	< r₂ (annulus)

6.3 Properties of Z-Transform

Property	Time Domain	z-Domain
Linearity	ax₁[n]+bx₂[n]	aX₁(z)+bX₂(z)
Time shifting	x[n-n₀]	z^{-n₀}X(z)
Frequency shifting	aⁿx[n]	X(z/a)
Time reversal	x[-n]	X(z⁻¹)
Convolution	x₁[n]*x₂[n]	X₁(z)X₂(z)
Differentiation	n x[n]	-z dX(z)/dz
Initial value	x[0] = lim_{z→∞} X(z)	–
Final value	lim_{n→∞}x[n]=lim_{z→1}(z-1)X(z)	(if stable)

6.4 Z-Transforms of Common Sequences

Sequence	Z-Transform	ROC
δ[n]	1	All z
δ[n-n₀]	z^{-n₀}	z ≠ 0
u[n]	1/(1-z^{-1}) = z/(z-1)		z	> 1
aⁿu[n]	1/(1-az^{-1}) = z/(z-a)		z	>	a
n aⁿu[n]	az^{-1}/(1-az^{-1})² = az/(z-a)²		z	>	a
-aⁿu[-n-1]	z/(z-a)		z	<	a
sin(Ωn)u[n]	z^{-1}sinΩ/(1-2z^{-1}cosΩ+z^{-2})		z	> 1
cos(Ωn)u[n]	(1-z^{-1}cosΩ)/(1-2z^{-1}cosΩ+z^{-2})		z	> 1
rⁿsin(Ωn)u[n]	r z^{-1}sinΩ/(1-2r z^{-1}cosΩ+r²z^{-2})		z	>	r
rⁿcos(Ωn)u[n]	(1-r z^{-1}cosΩ)/(1-2r z^{-1}cosΩ+r²z^{-2})		z	>	r

6.5 Solving Difference Equations using Z-Transform

Steps:

Take Z-transform of both sides
Use initial conditions
Solve for Y(z)
Take inverse Z-transform

7. System Analysis Using Transforms

7.1 Transfer Function

Continuous-Time (Laplace):

H(s) = Y(s)/X(s) = L[output]/L[input] (with zero initial conditions)

Discrete-Time (Z-Transform):

H(z) = Y(z)/X(z) = Z[output]/Z[input] (with zero initial conditions)

7.2 Frequency Response

From Laplace:

H(jω) = H(s)|_{s=jω}   (if ROC includes jω axis)

From Z-Transform:

H(e^{jΩ}) = H(z)|_{z=e^{jΩ}}   (if ROC includes unit circle)

7.3 System Stability

Criterion	Continuous-Time	Discrete-Time
BIBO stability	∫	h(t)	dt < ∞	Σ	h[n]	< ∞
Pole location (causal)	All poles in LHP (Re(s) < 0)	All poles inside unit circle (	z	< 1)
Marginal stability	Poles on jω axis (simple)	Poles on unit circle (simple)

7.4 Pole-Zero Plots

Feature	Interpretation
Poles (X)	Make H(s) or H(z) → ∞
Zeros (O)	Make H(s) or H(z) = 0
Stability	All poles in LHP (CT) or inside unit circle (DT)

8. Sampling Theorem

8.1 Statement

A bandlimited signal x(t) with maximum frequency ω_m (or f_m) can be perfectly reconstructed from its samples x[n] = x(nT) if the sampling frequency satisfies:

ω_s ≥ 2ω_m   (or f_s ≥ 2f_m)

where ω_s = 2π/T is the sampling frequency.

8.2 Nyquist Rate

Term	Definition
Nyquist rate	Minimum sampling rate = 2f_m
Nyquist frequency	Half the sampling rate = f_s/2
Aliasing	When f_s < 2f_m, high frequencies appear as low frequencies

8.3 Sampling in Frequency Domain

X_s(ω) = (1/T) Σ_{k=-∞}^{∞} X(ω - kω_s)

8.4 Ideal Reconstruction

Using low-pass filter with cutoff ω_c = ω_s/2:

x(t) = Σ_{n=-∞}^{∞} x[n] sinc(π(t-nT)/T)

9. Sample Exam Questions

Short Answer (5 marks each)

Distinguish between energy signals and power signals. Give an example of each.
State the sampling theorem. What is aliasing?
What is the difference between Fourier series and Fourier transform?
Distinguish between Laplace transform and Fourier transform.
What is the region of convergence (ROC) in Z-transform? Why is it important?

Numerical Problems (10-15 marks)

1. Convolution:
Compute y(t) = x(t) * h(t) where x(t) = u(t) – u(t-2) and h(t) = u(t) – u(t-1).

Solution:

x(t): 1 for 0<t<2, 0 elsewhere
h(t): 1 for 0<t<1, 0 elsewhere

For t < 0: y(t)=0
For 0 ≤ t < 1: y(t)=∫₀ᵗ 1·1 dτ = t
For 1 ≤ t < 2: y(t)=∫ₜ₋₁¹ 1·1 dτ = 1
For 2 ≤ t < 3: y(t)=∫ₜ₋₁² 1·1 dτ = 3-t
For t ≥ 3: y(t)=0

2. Fourier Transform:
Find the Fourier transform of x(t) = e^{-a|t|}, a > 0.

Solution:

X(ω) = ∫_{-∞}^{∞} e^{-a|t|} e^{-jωt} dt
= ∫_{-∞}^{0} e^{at} e^{-jωt} dt + ∫_{0}^{∞} e^{-at} e^{-jωt} dt
= ∫_{-∞}^{0} e^{(a-jω)t} dt + ∫_{0}^{∞} e^{-(a+jω)t} dt
= [e^{(a-jω)t}/(a-jω)]_{-∞}^{0} + [-e^{-(a+jω)t}/(a+jω)]_{0}^{∞}
= 1/(a-jω) + 1/(a+jω) = 2a/(a²+ω²)

3. Laplace Transform:
Solve y”(t) + 3y'(t) + 2y(t) = 0, y(0)=1, y'(0)=0.

Solution:

s²Y(s) - s·y(0) - y'(0) + 3[sY(s)-y(0)] + 2Y(s) = 0
s²Y(s) - s + 3sY(s) - 3 + 2Y(s) = 0
(s² + 3s + 2)Y(s) = s + 3
Y(s) = (s+3)/[(s+1)(s+2)] = 2/(s+1) - 1/(s+2)
y(t) = 2e^{-t} - e^{-2t}

Quick Revision Table – Transform Comparisons

Transform	Domain	Forward	Inverse	ROC	Use
Fourier	CT	∫x(t)e^{-jωt}dt	(1/2π)∫X(ω)e^{jωt}dω	All ω	Frequency analysis
DTFT	DT	Σx[n]e^{-jΩn}	(1/2π)∫X(e^{jΩ})e^{jΩn}dΩ		Frequency analysis (DT)
Laplace	CT	∫x(t)e^{-st}dt	(1/2πj)∫X(s)e^{st}ds	σ₁<Re(s)<σ₂	System analysis, ODEs
Z	DT	Σx[n]z^{-n}	(1/2πj)∮X(z)z^{n-1}dz	r₁<	z

TE-152 Electronic Devices & Circuits – Detailed Study Notes

These study notes are designed for undergraduate engineering students taking a course in Electronic Devices and Circuits. The notes cover the fundamental principles of semiconductor physics, diodes, bipolar junction transistors (BJTs), field effect transistors (FETs), transistor biasing, small-signal amplifiers, and power amplifiers.

1. Introduction to Semiconductor Physics

1.1 Atomic Structure and Energy Bands

Aspect	Detail
Energy bands	Valence band (electrons bound to atoms), Conduction band (free electrons), Forbidden gap (no energy states)
Conductors	No forbidden gap (overlapping bands)
Semiconductors	Small forbidden gap (≈1.1 eV for Si, 0.7 eV for Ge)
Insulators	Large forbidden gap (>3 eV)

1.2 Intrinsic Semiconductors

Aspect	Detail
Definition	Pure semiconductor with no impurities
Carriers	Equal number of electrons and holes
Carrier concentration	nᵢ = pᵢ = BT^{3/2} e^{-E_g/2kT}
For Si at 300K	nᵢ ≈ 1.5 × 10¹⁰ cm⁻³

1.3 Extrinsic Semiconductors

Type	Doping	Majority Carriers	Minority Carriers	Donor/Acceptor Concentration
n-type	Pentavalent (P, As, Sb)	Electrons	Holes	N_D ≈ N_D⁺
p-type	Trivalent (B, Al, Ga)	Holes	Electrons	N_A ≈ N_A⁻

Mass Action Law:

n × p = nᵢ²

For n-type: n ≈ N_D, p ≈ nᵢ²/N_D

For p-type: p ≈ N_A, n ≈ nᵢ²/N_A

1.4 Carrier Transport Mechanisms

Mechanism	Description	Current Density
Drift	Movement due to electric field	J_drift = q(μ_n n + μ_p p)E
Diffusion	Movement due to concentration gradient	J_diff = qD_n (dn/dx) – qD_p (dp/dx)
Einstein relation	D/μ = kT/q (at room temperature ≈ 26 mV)

2. Semiconductor Diodes

2.1 p-n Junction Diode

Aspect	Detail
Structure	p-type and n-type semiconductor regions
Depletion region	Region devoid of free carriers, built-in potential
Built-in potential (V_bi)	V_bi = (kT/q) ln(N_A N_D / nᵢ²)

Biasing Conditions:

Biasing	Connection	Depletion Width	Current	Diode State
Forward bias	p (+), n (-)	Decreases	Large (exponential)	ON
Reverse bias	p (-), n (+)	Increases	Small (leakage)	OFF
Zero bias	No external voltage	Equilibrium	Zero	–

2.2 Diode V-I Characteristics

Shockley Diode Equation:

I_D = I_S (e^{V_D/(ηV_T)} - 1)

where:

I_S = reverse saturation current (typically 10⁻¹² to 10⁻⁶ A)
V_T = thermal voltage = kT/q ≈ 26 mV at 300K
η = ideality factor (≈1 for ideal, 1-2 for practical)

Cut-in Voltage (V_γ):

Silicon: 0.6 – 0.7 V
Germanium: 0.2 – 0.3 V
Schottky: 0.2 – 0.4 V

2.3 Diode Resistance

Resistance	Definition	Formula
DC (static) resistance	R_DC = V_D / I_D	–
AC (dynamic) resistance	r_d = dV_D/dI_D = ηV_T / I_D	~26 mV / I_D (mA)
Reverse resistance	R_R = V_R / I_R	Very large (MΩ)

2.4 Diode Capacitances

Type	Origin	Formula	Dominant Bias
Junction (depletion) capacitance	Charge variation in depletion region	C_j = C_{j0} / √(1 + V_R/V_bi)	Reverse bias
Diffusion capacitance	Charge storage in neutral regions	C_d = τ × (dI_D/dV_D) = τ × I_D/(ηV_T)	Forward bias

2.5 Diode Breakdown Mechanisms

Mechanism	Description	Temperature Coefficient	Occurs In
Zener breakdown	High electric field → tunneling	Negative	Heavily doped diodes (<5V)
Avalanche breakdown	Impact ionization	Positive	Lightly doped diodes (>6V)

2.6 Special Purpose Diodes

Diode Type	Symbol Feature	Characteristics	Applications
Zener diode	Bent line on cathode	Operates in reverse breakdown	Voltage regulation
Light Emitting Diode (LED)	Arrows pointing away	Emits light when forward biased	Indicators, displays
Photodiode	Arrows pointing toward	Light-sensitive reverse current	Light detection, sensors
Schottky diode	S-like symbol	Low forward voltage, fast switching	High-frequency circuits
Varactor (Varicap) diode	Capacitor-like symbol	Junction capacitance varies with voltage	Tuning circuits
Tunnel diode		Negative resistance region	High-frequency oscillators

2.7 Diode Applications

Rectifiers:

Type	Circuit	V_dc (avg)	PIV	Ripple Frequency	Efficiency
Half-wave	1 diode	V_m/π	V_m	f_in	40.6%
Full-wave (center-tapped)	2 diodes	2V_m/π	2V_m	2f_in	81.2%
Full-wave (bridge)	4 diodes	2V_m/π	V_m	2f_in	81.2%

Filters:

Filter	Components	Ripple Factor
Capacitor	C only	1/(2√3 f R_L C)
LC	L + C	√3/(2) × (X_C/X_L)
π (CLC)	C1 + L + C2	Very low

Clippers (Limiters):

Series positive clipper
Series negative clipper
Shunt positive clipper
Shunt negative clipper
Biased clippers

Clampers (DC Restorers):

Positive clamper
Negative clamper
Biased clampers

Voltage Multipliers:

Voltage doubler (half-wave, full-wave)
Voltage tripler
Voltage quadrupler

Zener Voltage Regulator:

V_out = V_Z
I_S = (V_in - V_Z)/R_S
I_Z = I_S - I_L
Condition: I_Z(min) < I_Z < I_Z(max)

3. Bipolar Junction Transistors (BJTs)

3.1 BJT Structure and Symbols

Type	Structure	Layers	Terminals	Arrow Direction
npn	n-p-n	Emitter (n), Base (p), Collector (n)	E, B, C	Emitter arrow out
pnp	p-n-p	Emitter (p), Base (n), Collector (p)	E, B, C	Emitter arrow in

3.2 BJT Modes of Operation

Mode	BE Junction	BC Junction	Applications
Cut-off	Reverse	Reverse	Switch OFF
Active (Forward active)	Forward	Reverse	Amplifier
Saturation	Forward	Forward	Switch ON
Reverse active	Reverse	Forward	Rarely used

3.3 BJT Current Relationships

I_E = I_B + I_C
I_C = β I_B   (DC current gain, typical 50-300)
I_C = α I_E   (α = β/(β+1) ≈ 1)
β = α/(1-α)
I_E = (β+1) I_B

3.4 BJT Configurations

Configuration	Input	Output	Current Gain	Voltage Gain	Input Z	Output Z	Phase Shift
Common Emitter (CE)	Base	Collector	High (β)	High	Medium	Medium	180°
Common Collector (CC)	Base	Emitter	High (β+1)	≈ 1	High	Low	0°
Common Base (CB)	Emitter	Collector	≈ 1	High	Low	High	0°

3.5 BJT Characteristics

Input (Base) Characteristics:

I_B vs. V_BE at constant V_CE
Similar to diode characteristic
V_BE ≈ 0.6-0.7 V (Si) in active region

Output (Collector) Characteristics:

I_C vs. V_CE at constant I_B
Three regions: cut-off, active, saturation
Early effect: I_C increases slightly with V_CE

Early Voltage (V_A):

Slope of I_C vs. V_CE in active region
I_C = I_S e^{V_BE/V_T} (1 + V_CE/V_A)

3.6 BJT Biasing Circuits

Biasing Method	Stability	Complexity	Applications
Fixed bias	Poor	Simple	Switching
Emitter bias	Fair	Simple	Basic amplifiers
Voltage divider bias	Excellent	Moderate	Most common
Collector feedback bias	Good	Moderate	Simple amplifiers

Voltage Divider Bias Design:

V_B = (R2/(R1+R2)) × V_CC
V_E = V_B - V_BE
I_E = V_E / R_E
I_C ≈ I_E
V_C = V_CC - I_C × R_C
V_CE = V_C - V_E

3.7 BJT as a Switch

State	V_BE	I_B	I_C	V_CE	Condition
Cut-off (OFF)	< 0.6 V	0	0	V_CC	V_in low
Saturation (ON)	≈ 0.7 V	≥ I_C/β	V_CC/R_C	≈ 0.2 V	V_in high

Design for Saturation:

I_C(sat) = V_CC / R_C
I_B(min) = I_C(sat) / β
R_B = (V_in - V_BE) / I_B (use I_B = 2-5× I_B(min) for hard saturation)

3.8 BJT Small-Signal Model (Hybrid-π)

Model Parameters:

g_m = I_C / V_T (transconductance)
r_π = β / g_m (base-emitter resistance)
r_o = V_A / I_C (output resistance, often neglected)
C_π = C_JE + τ_F × g_m (base-emitter capacitance)
C_μ = C_JC (base-collector capacitance)

Hybrid-π Equivalent Circuit:

Base  ──ww───┬───┬── Collector
            r_π   │
              │   │
              └───┼─── g_m·V_π ──┬─── r_o ──┐
                  │              │          │
                  └──────────────┴──────────┘
                 Emitter

3.9 BJT Amplifiers (Small-Signal Analysis)

Common Emitter Amplifier:

Voltage gain: A_v = -g_m (R_C || r_o)
Input impedance: Z_in = R1 || R2 || r_π
Output impedance: Z_out = R_C || r_o
Current gain: A_i = β

Common Collector (Emitter Follower):

Voltage gain: A_v ≈ 1
Input impedance: Z_in = R1 || R2 || (β+1)(R_E || R_L)
Output impedance: Z_out = R_E || (r_π/(β+1))

Common Base Amplifier:

Voltage gain: A_v = g_m (R_C || r_o)
Input impedance: Z_in = R_E || (r_π/(β+1))
Output impedance: Z_out = R_C || r_o
Current gain: A_i ≈ 1

4. Field Effect Transistors (FETs)

4.1 JFET (Junction Field Effect Transistor)

Aspect	Detail
Structure	n-channel or p-channel with gate-source junction
Terminals	Source (S), Gate (G), Drain (D)
Operation	Voltage-controlled device (V_GS controls channel resistance)
Shockley’s equation	I_D = I_DSS (1 – V_GS/V_P)²

JFET Regions:

Region	Condition	Application
Ohmic (Triode)	V_DS small, V_GS > V_P	Voltage-controlled resistor
Saturation (Pinch-off)	V_DS ≥ V_GS – V_P	Amplifier
Cut-off	V_GS ≤ V_P	Switch OFF

4.2 MOSFET (Metal Oxide Semiconductor FET)

Type	Enhancement Mode (normally off)	Depletion Mode (normally on)
n-channel	V_GS > V_TH to turn on	V_GS < 0 to turn off
p-channel	V_GS < V_TH to turn on	V_GS > 0 to turn off

MOSFET Regions:

Region	Condition	Application
Cut-off	V_GS < V_TH	Switch OFF
Triode (Ohmic)	V_GS > V_TH, V_DS < V_GS – V_TH	Voltage-controlled resistor
Saturation	V_GS > V_TH, V_DS ≥ V_GS – V_TH	Amplifier

MOSFET Equations:

Triode region: I_D = K [2(V_GS – V_TH)V_DS – V_DS²]
Saturation region: I_D = K (V_GS – V_TH)² (where K = (1/2)μ_n C_ox (W/L))

4.3 FET vs. BJT Comparison

Parameter	BJT	JFET	MOSFET
Control	Current-controlled (I_B)	Voltage-controlled (V_GS)	Voltage-controlled (V_GS)
Input impedance	Low (1-5 kΩ)	High (MΩ)	Very high (10⁹-10¹⁵ Ω)
Gain	High (β=50-300)	Low (g_m=1-10 mS)	Low to moderate
Noise	Moderate	Low	Low
Temperature stability	Poor	Good	Good
Switching speed	Moderate	Slow	Fast
Fabrication	Bipolar	JFET process	CMOS

4.4 FET Biasing

Biasing Method	Application
Fixed bias	Simple, poor stability
Self-bias	Common for JFETs
Voltage divider bias	Most stable
Current source bias	Best stability (ICs)

JFET Self-Bias:

V_GS = -I_D R_S
I_D = I_DSS (1 - V_GS/V_P)²
Solve for I_D and V_GS

4.5 FET Small-Signal Model

Parameters:

g_m = ∂I_D/∂V_GS = (2I_DSS/|V_P|)(1 - V_GS/V_P) = (2I_D)/|V_GS - V_P|
r_d = ∂V_DS/∂I_D = V_A/I_D (output resistance)

Small-Signal Equivalent Circuit:

Gate ──────┬───┬── Drain
           │   │
           │   └─── g_m·V_GS ──┬─── r_d ──┐
           │                  │          │
           └──────────────────┴──────────┘
          Source

4.6 FET Amplifiers

Configuration	Voltage Gain	Input Impedance	Output Impedance
Common Source (CS)	-g_m(R_D		r_d)	Very high	R_D	r_d
Common Drain (CD)	≈ 1	Very high	1/g_m		R_S
Common Gate (CG)	g_m(R_D		r_d)	1/g_m	R_D	r_d

5. Multistage Amplifiers

5.1 Coupling Methods

Method	Frequency Response	Advantages	Disadvantages
RC coupling	Bandpass (blocks DC)	Simple, cheap	Low frequency cut-off
Direct coupling	DC to high frequency	Good for ICs	DC drift
Transformer coupling	Bandpass	Impedance matching	Expensive, bulky

5.2 Cascade Amplifier Gain

A_v(total) = A_v1 × A_v2 × A_v3 × ...

5.3 Darlington Pair

Aspect	Detail
Configuration	Two BJTs connected with collectors common, emitter of first to base of second
Current gain	β_D = β₁ × β₂ (very high)
Input impedance	Z_in ≈ β₁ × β₂ × R_E (very high)
Output impedance	Low
Applications	Buffers, high-gain stages

6. Power Amplifiers

6.1 Classification by Conduction Angle

Class	Conduction Angle	Efficiency	Distortion	Applications
A	360°	25% (max)	Low	Small-signal, low power
B	180°	78.5%	Moderate	Push-pull audio
AB	180-360°	50-70%	Low	High-fidelity audio
C	<180°	>80%	High	RF amplifiers
D	Switching	>90%	Low (filtered)	Digital audio

6.2 Class A Amplifier

Single-ended:

Q-point at center of load line
Maximum efficiency = 25%
Output power = I_CQ² × R_L / 2

6.3 Class B Push-Pull Amplifier

Aspect	Detail
Configuration	Two complementary transistors (npn and pnp)
Operation	Each conducts for 180°
Crossover distortion	Occurs near zero crossing
Maximum efficiency	78.5%
Output power	V_CC²/(2R_L) (peak)

6.4 Class AB Amplifier

Biased slightly above cut-off to eliminate crossover distortion
Compromise between efficiency and distortion

6.5 Heat Sinks and Power Dissipation

Thermal Resistance:

θ_JA = θ_JC + θ_CS + θ_SA
T_J = T_A + P_D × θ_JA
where:
θ_JC = junction-to-case, θ_CS = case-to-sink, θ_SA = sink-to-ambient

7. Sample Exam Questions

Short Answer (5 marks each)

Distinguish between intrinsic and extrinsic semiconductors. Explain doping.
Draw and explain the V-I characteristics of a p-n junction diode. Mark the cut-in voltage and breakdown voltage.
Explain the three regions of operation of a BJT.
Distinguish between BJT and MOSFET.
What are the advantages of Class B push-pull amplifier over Class A?

Numerical Problems (10-15 marks)

1. Diode Circuit:
For the circuit shown, find I_D and V_D. Assume Si diode (V_γ=0.7V), V_CC=10V, R=1kΩ.

Solution:

Assuming diode is forward biased:
V_D = 0.7 V
I_D = (V_CC - V_D)/R = (10 - 0.7)/1000 = 9.3 mA
Check: I_D > 0, assumption correct.

2. BJT Biasing:
For the voltage divider bias circuit: V_CC=12V, R1=47kΩ, R2=10kΩ, R_C=2.2kΩ, R_E=1kΩ, β=100. Find V_B, V_E, I_C, V_C, V_CE.

Solution:

V_B = (R2/(R1+R2)) × V_CC = (10/57) × 12 = 2.105 V
V_E = V_B - V_BE = 2.105 - 0.7 = 1.405 V
I_E = V_E/R_E = 1.405/1000 = 1.405 mA
I_C ≈ I_E = 1.405 mA
V_C = V_CC - I_C×R_C = 12 - 1.405×2.2 = 12 - 3.091 = 8.909 V
V_CE = V_C - V_E = 8.909 - 1.405 = 7.504 V

3. CE Amplifier Gain:
For the CE amplifier above, find voltage gain A_v = v_out/v_in. Assume r_o = ∞, V_T=26mV.

Solution:

r_e = V_T/I_E = 26/1.405 = 18.5 Ω
A_v = -R_C/r_e = -2200/18.5 = -119

4. Class A Amplifier Power:
A Class A amplifier has V_CC=12V, I_CQ=100mA, R_L=100Ω. Find output power, input power, and efficiency.

Solution:

V_CEQ = V_CC/2 = 6V (for maximum swing)
P_out(max) = I_CQ² × R_L/2 = (0.1)² × 100/2 = 0.5 W
P_in = V_CC × I_CQ = 12 × 0.1 = 1.2 W
η = P_out/P_in = 0.5/1.2 = 41.7%
(Note: theoretical max for Class A is 25% when R_L is transformer coupled)

Quick Revision Table – Diode Parameters

Parameter	Silicon	Germanium	Schottky
Cut-in voltage	0.6-0.7 V	0.2-0.3 V	0.2-0.4 V
Reverse leakage	nA-μA	μA	μA-mA
Reverse recovery time	μs-ns	μs	ns
Max temperature	150-200°C	75-100°C	125-150°C

Quick Revision Table – BJT Configurations

Parameter	CE	CC	CB
Voltage gain	High	≈1	High
Current gain	High (β)	High (β+1)	≈1
Input impedance	Medium	High	Low
Output impedance	Medium	Low	High
Phase shift	180°	0°	0°

Quick Revision Table – FET Configurations

Parameter	CS	CD	CG
Voltage gain	High	≈1	High
Current gain	High	High	≈1
Input impedance	Very high	Very high	Low
Output impedance	Medium	Low	High
Phase shift	180°	0°	0°

TE-252: Microprocessors & Microcontroller Systems

Here are detailed study notes for TE-252: Microprocessors & Microcontroller Systems, written from an Electrical/Computer Engineering perspective. These notes cover the fundamental principles of microprocessors and microcontrollers—architecture, instruction sets, programming, memory interfacing, I/O interfacing, interrupts, and applications. The emphasis is on understanding how microprocessors execute instructions and how microcontrollers are used in embedded systems.

1. Introduction to Microprocessors and Microcontrollers

1.1. What is a Microprocessor?

A microprocessor is a programmable integrated circuit that performs arithmetic, logic, control, and input/output operations. It is the central processing unit (CPU) of a computer system on a single chip.

The Core Question: How does a microprocessor fetch, decode, and execute instructions to perform computational tasks?

1.2. What is a Microcontroller?

A microcontroller is a complete computer system on a single chip, containing a microprocessor core, memory (RAM, ROM/Flash), and I/O peripherals (timers, ADC, serial communication, etc.).

1.3. Microprocessor vs. Microcontroller

Feature	Microprocessor	Microcontroller
Components	CPU only	CPU + RAM + ROM + I/O
Memory	External (RAM, ROM)	Internal (on-chip)
I/O Ports	External	Built-in
Power consumption	Higher	Lower
Cost	Higher (system cost)	Lower
Applications	Computers, tablets, smartphones	Embedded systems, appliances
Examples	Intel 8085, 8086, x86, ARM Cortex-A	8051, PIC, AVR, ARM Cortex-M

1.4. Evolution of Microprocessors

Generation	Year	Word Size	Example	Transistors
1st	1971	4-bit	Intel 4004	2,300
2nd	1972	8-bit	Intel 8008	3,500
3rd	1974	8-bit	Intel 8080	6,000
4th	1978	16-bit	Intel 8086	29,000
5th	1985	32-bit	Intel 80386	275,000
6th	1993	32/64-bit	Pentium	3.1 million
Modern	2000+	64-bit	Core i9, ARM	billions

2. Microprocessor Architecture

2.1. Basic Block Diagram

┌─────────────────────────────────────────────────────────────┐
│                      Microprocessor                          │
│  ┌─────────────┐    ┌─────────────┐    ┌─────────────┐     │
│  │     ALU     │    │  Registers  │    │  Control    │     │
│  │  (Arithmetic │    │             │    │   Unit      │     │
│  │   Logic     │    │             │    │             │     │
│  │   Unit)     │    │             │    │             │     │
│  └──────┬──────┘    └──────┬──────┘    └──────┬──────┘     │
│         │                  │                  │             │
│         └──────────────────┼──────────────────┘             │
│                            │                                │
│                   ┌────────▼────────┐                       │
│                   │   Internal Bus  │                       │
│                   └────────┬────────┘                       │
│                            │                                │
│         ┌──────────────────┼──────────────────┐             │
│         │                  │                  │             │
│    ┌────▼────┐        ┌────▼────┐        ┌────▼────┐        │
│    │Address  │        │ Data    │        │Control  │        │
│    │Buffer   │        │ Buffer  │        │Buffer   │        │
│    └────┬────┘        └────┬────┘        └────┬────┘        │
└─────────┼──────────────────┼──────────────────┼─────────────┘
          │                  │                  │
    Address Bus           Data Bus           Control Bus

2.2. System Bus

Bus	Direction	Width	Function
Address Bus	Unidirectional (MPU → Memory/I/O)	16-bit (8085), 20-bit (8086)	Selects memory location or I/O device
Data Bus	Bidirectional	8-bit (8085), 16-bit (8086)	Transfers data between MPU and memory/I/O
Control Bus	Various	Various	Control signals (RD, WR, IO/M, etc.)

Memory addressing capability:

$Addressable locations = 2^{n}$

Where $n$ = number of address lines

2.3. Registers

Types of Registers:

Type	Function	Examples
Accumulator	Stores results of ALU operations	A (8085), EAX (x86)
General Purpose	Store temporary data	B, C, D, E, H, L (8085)
Program Counter (PC)	Holds address of next instruction	PC (16-bit)
Stack Pointer (SP)	Points to top of stack	SP (16-bit)
Instruction Register (IR)	Holds current instruction	IR
Flag/Status Register	Stores condition flags	F (8085), EFLAGS (x86)

2.4. Flags (Status Register)

Flag	Function	Set When
Zero (Z)	Result is zero	Result = 0
Carry (CY)	Carry from MSB	Addition carry or subtraction borrow
Sign (S)	Result is negative	MSB = 1 (in signed operations)
Parity (P)	Even number of 1s	Result has even parity
Auxiliary Carry (AC)	Carry from bit 3 to 4	BCD operations
Overflow (O)	Signed overflow	For signed arithmetic

3. The 8085 Microprocessor (8-bit)

3.1. 8085 Architecture

┌─────────────────────────────────────────────────────────────┐
│                        Intel 8085                            │
│                                                              │
│  ┌─────────┐    ┌─────────┐    ┌─────────┐    ┌─────────┐   │
│  │   A     │    │   B     │    │   C     │    │   D     │   │
│  │(Acc)    │    │         │    │         │    │         │   │
│  └─────────┘    └─────────┘    └─────────┘    └─────────┘   │
│  ┌─────────┐    ┌─────────┐    ┌─────────┐    ┌─────────┐   │
│  │   E     │    │   H     │    │   L     │    │  Flags  │   │
│  │         │    │         │    │         │    │   F     │   │
│  └─────────┘    └─────────┘    └─────────┘    └─────────┘   │
│                                                              │
│  ┌─────────────────────────────────────────────────────┐   │
│  │                  ALU (Arithmetic Logic Unit)         │   │
│  └─────────────────────────────────────────────────────┘   │
│                                                              │
│  ┌─────────┐    ┌─────────┐    ┌─────────────────────────┐ │
│  │   PC    │    │   SP    │    │   Instruction Register  │ │
│  │(16-bit) │    │(16-bit) │    │         (IR)            │ │
│  └─────────┘    └─────────┘    └─────────────────────────┘ │
│                                                              │
│  ┌─────────────────────────────────────────────────────┐   │
│  │                 Control Unit                         │   │
│  │          (Instruction Decoder & Timing)              │   │
│  └─────────────────────────────────────────────────────┘   │
└─────────────────────────────────────────────────────────────┘

3.2. 8085 Pin Diagram (Brief)

Pin	Function	Pin	Function
AD0-AD7	Multiplexed Address/Data	A8-A15	Higher address lines
ALE	Address Latch Enable	RD	Read control
WR	Write control	IO/M	I/O or Memory select
S0, S1	Status signals	READY	Wait state
RESET IN/OUT	Reset	CLK	Clock output
INTR, RST 5.5-7.5	Interrupts	HOLD, HLDA	DMA control

3.3. 8085 Instruction Set

Data Transfer Instructions:

Instruction	Operation	Description
MOV Rd, Rs	Rd ← Rs	Copy register to register
MOV Rd, M	Rd ← [HL]	Copy memory to register
MOV M, Rs	[HL] ← Rs	Copy register to memory
MVI Rd, data	Rd ← data	Move immediate
LXI Rp, data16	Rp ← data16	Load register pair immediate
LDA addr	A ← [addr]	Load accumulator direct
STA addr	[addr] ← A	Store accumulator direct
XCHG	HL ←→ DE	Exchange register pairs

Arithmetic Instructions:

Instruction	Operation	Description
ADD R	A ← A + R	Add register to accumulator
ADI data	A ← A + data	Add immediate
ADC R	A ← A + R + CY	Add with carry
SUB R	A ← A – R	Subtract register
SUI data	A ← A – data	Subtract immediate
SBB R	A ← A – R – CY	Subtract with borrow
INR R	R ← R + 1	Increment register
DCR R	R ← R – 1	Decrement register
INX Rp	Rp ← Rp + 1	Increment register pair
DCX Rp	Rp ← Rp – 1	Decrement register pair

Logical Instructions:

Instruction	Operation	Description
ANA R	A ← A & R	AND with register
ANI data	A ← A & data	AND immediate
ORA R	A ← A	R	OR with register
ORI data	A ← A	data	OR immediate
XRA R	A ← A ⊕ R	XOR with register
XRI data	A ← A ⊕ data	XOR immediate
CMA	A ← ~A	Complement accumulator
RLC	Rotate left	A ← A rotated left
RRC	Rotate right	A ← A rotated right

Branch Instructions:

Instruction	Operation	Description
JMP addr	PC ← addr	Unconditional jump
JZ addr	PC ← addr if Z=1	Jump if zero
JNZ addr	PC ← addr if Z=0	Jump if not zero
JC addr	PC ← addr if CY=1	Jump if carry
JNC addr	PC ← addr if CY=0	Jump if no carry
CALL addr	SP ← SP-2, [SP] ← PC, PC ← addr	Call subroutine
RET	PC ← [SP], SP ← SP+2	Return from subroutine

Stack Instructions:

Instruction	Operation	Description
PUSH Rp	SP ← SP-2, [SP] ← Rp	Push register pair
POP Rp	Rp ← [SP], SP ← SP+2	Pop register pair
PUSH PSW	Save accumulator and flags	Push processor status
POP PSW	Restore accumulator and flags	Pop processor status

3.4. Addressing Modes of 8085

Mode	Description	Example
Immediate	Data is part of instruction	MVI A, 05H
Register	Data in register	MOV B, A
Direct	Address in instruction	LDA 2000H
Indirect	Address in register pair	MOV A, M (HL points to address)
Implied	Implicit register	CMA

3.5. Timing Diagram

Machine Cycles:

Cycle	T-states	Operation
Opcode Fetch (OF)	4-6	Fetch instruction opcode
Memory Read (MR)	3	Read from memory
Memory Write (MW)	3	Write to memory
I/O Read (IOR)	3	Read from I/O port
I/O Write (IOW)	3	Write to I/O port

T-states:

One clock period = 1 T-state
Each machine cycle consists of 3-6 T-states

4. 8051 Microcontroller

4.1. 8051 Architecture

┌─────────────────────────────────────────────────────────────┐
│                      8051 Microcontroller                    │
│                                                              │
│  ┌─────────┐    ┌─────────┐    ┌─────────┐    ┌─────────┐   │
│  │   A     │    │   B     │    │   R0    │    │   R1    │   │
│  └─────────┘    └─────────┘    └─────────┘    └─────────┘   │
│  ┌─────────┐    ┌─────────┐    ┌─────────┐    ┌─────────┐   │
│  │   R2    │    │   R3    │    │   R4    │    │   R5    │   │
│  └─────────┘    └─────────┘    └─────────┘    └─────────┘   │
│  ┌─────────┐    ┌─────────┐    ┌─────────┐    ┌─────────┐   │
│  │   R6    │    │   R7    │    │   DPTR  │    │   PC    │   │
│  └─────────┘    └─────────┘    └─────────┘    └─────────┘   │
│                                                              │
│  ┌─────────────────────────────────────────────────────┐   │
│  │                  ALU & Control Unit                  │   │
│  └─────────────────────────────────────────────────────┘   │
│                                                              │
│  ┌─────────────┐    ┌─────────────┐    ┌─────────────┐     │
│  │  4KB ROM    │    │  128B RAM   │    │   Timers    │     │
│  │  (Internal) │    │  (Internal) │    │  (2×16-bit) │     │
│  └─────────────┘    └─────────────┘    └─────────────┘     │
│                                                              │
│  ┌─────────────┐    ┌─────────────┐    ┌─────────────┐     │
│  │   Serial    │    │   I/O Ports │    │  Interrupt  │     │
│  │   Port      │    │  (4×8-bit)  │    │   System    │     │
│  └─────────────┘    └─────────────┘    └─────────────┘     │
└─────────────────────────────────────────────────────────────┘

4.2. 8051 Memory Organization

Program Memory (ROM):

Internal: 4KB (0000H – 0FFFH)
External: Up to 64KB (0000H – FFFFH)

Data Memory (RAM):

Internal: 128 bytes (00H – 7FH)
Special Function Registers (80H – FFH)
External: Up to 64KB

Register Banks (Internal RAM 00H-1FH):

Bank	Address Range	Registers
Bank 0	00H-07H	R0-R7
Bank 1	08H-0FH	R0-R7
Bank 2	10H-17H	R0-R7
Bank 3	18H-1FH	R0-R7

4.3. 8051 I/O Ports

Port	Address	Pins	Features
Port 0	80H	32-39	Open drain, multiplexed address/data
Port 1	90H	1-8	General purpose I/O
Port 2	A0H	21-28	General purpose, high address byte
Port 3	B0H	10-17	General purpose + alternate functions

Port 3 Alternate Functions:

Pin	Function	Description
P3.0	RXD	Serial input
P3.1	TXD	Serial output
P3.2	INT0	External interrupt 0
P3.3	INT1	External interrupt 1
P3.4	T0	Timer 0 external input
P3.5	T1	Timer 1 external input
P3.6	WR	External memory write
P3.7	RD	External memory read

4.4. 8051 Instruction Set Examples

Data Transfer:

MOV A, #55H    ; Load accumulator with 55H
MOV R0, A      ; Copy A to R0
MOV @R0, A     ; Store A at address in R0
MOV DPTR, #2000H ; Load data pointer
MOVX @DPTR, A  ; Store A to external memory

Arithmetic:

ADD A, R0      ; A = A + R0
ADDC A, #10    ; A = A + 10 + Carry
SUBB A, R1     ; A = A - R1 - Borrow
INC DPTR       ; Increment data pointer
MUL AB         ; Multiply A × B (result in A and B)

Logical:

ANL A, #0FH    ; Mask upper nibble
ORL P1, #03H   ; Set bits 0 and 1 of Port 1
XRL A, R2      ; XOR with R2
RL A           ; Rotate left
RR A           ; Rotate right
SWAP A         ; Swap nibbles

Branch:

LJMP START     ; Long jump
SJMP LOOP      ; Short jump
JZ LABEL       ; Jump if A = 0
JNZ LABEL      ; Jump if A ≠ 0
CJNE A, #55H, LABEL  ; Compare and jump
DJNZ R7, LOOP  ; Decrement R7, jump if not zero
LCALL SUB      ; Long call
RET            ; Return

4.5. 8051 Timers

Timer Modes:

Mode	Size	Function
Mode 0	13-bit	8192 count
Mode 1	16-bit	65536 count
Mode 2	8-bit auto-reload	256 count
Mode 3	Two 8-bit timers (Timer 0 only)	Split

Timer Registers:

TMOD: Timer mode register
TCON: Timer control register
TH0/TL0: Timer 0 high/low bytes
TH1/TL1: Timer 1 high/low bytes

Timer Calculation:

$Count = Clock period \times 12 Delay$ $Initial value = Max count - Desired count$

4.6. 8051 Serial Communication

Serial Modes:

Mode	Baud Rate	Data Bits	Description
0	fosc/12	8	Shift register
1	Variable	8	8-bit UART
2	fosc/32 or fosc/64	9	9-bit UART
3	Variable	9	9-bit UART

Baud Rate Calculation (Mode 1,3):

$Baud Rate = 322 ^{SMOD} \times 12 \times ( 256 - T H 1 ) f ^{osc}$

Serial Registers:

SBUF: Serial buffer (transmit/receive)
SCON: Serial control register

5. ARM Cortex-M Microcontroller

5.1. ARM Architecture Overview

ARM (Advanced RISC Machines):

RISC architecture
Low power consumption
Dominant in embedded and mobile devices

ARM Cortex Families:

Family	Performance	Applications
Cortex-A	High	Application processors (smartphones, tablets)
Cortex-R	Real-time	Real-time systems (automotive, medical)
Cortex-M	Low power	Microcontrollers (IoT, embedded)

5.2. Cortex-M0/M3/M4 Features

Feature	Cortex-M0	Cortex-M3	Cortex-M4
Pipeline	3-stage	3-stage	3-stage
DMIPS/MHz	0.9	1.25	1.25
Thumb/Thumb-2	Thumb	Thumb-2	Thumb-2
DSP instructions	No	No	Yes
FPU	No	No	Optional
MPU	No	Yes	Yes

5.3. ARM Registers

16 General Purpose Registers (R0-R15):

Register	Function
R0-R12	General purpose
R13 (SP)	Stack Pointer
R14 (LR)	Link Register (return address)
R15 (PC)	Program Counter

Program Status Register (PSR):

Contains condition flags (N, Z, C, V)
Execution state bits (Thumb mode)
Interrupt mask bits

5.4. Thumb-2 Instruction Set

Features:

16-bit and 32-bit instructions
Improved code density
Full access to ARM functionality

Example Instructions:

MOV R0, #0x55      ; Load immediate
ADD R1, R2, R3     ; R1 = R2 + R3
LDR R0, [R1]       ; Load from address in R1
STR R0, [R1]       ; Store to address in R1
B LABEL            ; Branch
BL FUNCTION        ; Branch with link (call)
BX LR              ; Return

6. Memory Interfacing

6.1. Memory Types

Type	Volatile	Read/Write	Speed	Use
SRAM	Yes	Read/Write	Fast	Cache, data memory
DRAM	Yes	Read/Write	Moderate	Main memory
ROM	No	Read only	Slow	Program storage
EPROM	No	UV erasable	Slow	Development
EEPROM	No	Electrically erasable	Slow	Configuration
Flash	No	Block erasable	Moderate	Program storage

6.2. Address Decoding

Simple NAND Decoder:

Uses NAND gates to select chip when specific address appears

3-to-8 Decoder (74LS138):

Generates 8 chip select signals from 3 address lines

Partial Decoding:

Uses fewer address lines (waste of address space)

Full Decoding:

Uses all address lines (unique address per chip)

6.3. Memory Interfacing Example (8085)

Interfacing 8KB RAM (2×4KB RAM chips):

Address range: 0000H – 1FFFH (8KB)
Chip 1: 0000H – 0FFFH (4KB)
Chip 2: 1000H – 1FFFH (4KB)

Chip select logic:

CS1 = A15·A14·A13·A12
CS2 = A15·A14·A13·Ā12

7. I/O Interfacing

7.1. I/O Addressing Methods

Method	Description	Example
Memory-mapped I/O	I/O devices share memory address space	8085 (IO/M=0)
Isolated I/O	Separate I/O address space	8085 (IO/M=1)

7.2. 8255 Programmable Peripheral Interface (PPI)

Features:

24 I/O pins (3 ports × 8 bits)
3 operating modes

Ports:

Port	I/O Lines	Address
Port A	8	Base
Port B	8	Base+1
Port C	8	Base+2
Control Register	—	Base+3

Modes:

Mode	Description
Mode 0 (Basic I/O)	Simple input/output
Mode 1 (Strobed I/O)	Handshaking signals
Mode 2 (Bidirectional)	Bi-directional bus (Port A only)

7.3. 8254 Programmable Interval Timer

Features:

3 independent 16-bit counters
6 operating modes

Modes:

Mode	Function
0	Interrupt on terminal count
1	Hardware retriggerable one-shot
2	Rate generator
3	Square wave generator
4	Software triggered strobe
5	Hardware triggered strobe

7.4. 8259 Programmable Interrupt Controller (PIC)

Features:

Manages up to 8 interrupt inputs
Prioritizes interrupts
Cascadable for 64 interrupts

8. Interrupts

8.1. Interrupt Types

Type	Source	Description
Hardware Interrupt	External device	IRQ, INT pins
Software Interrupt	Program instruction	INT, TRAP
Internal Interrupt	CPU condition	Divide by zero

8.2. 8085 Interrupts

Interrupt	Priority	Maskable	Vector Address
TRAP	Highest	No	0024H
RST 7.5		Yes	003CH
RST 6.5		Yes	0034H
RST 5.5		Yes	002CH
INTR	Lowest	Yes	User defined

Interrupt Handling:

Complete current instruction
Push PC onto stack
Jump to interrupt vector address
Execute ISR
Return (RET instruction restores PC)

8.3. 8051 Interrupts

Interrupt	Vector Address	Priority
RESET	0000H	Highest
External INT0	0003H
Timer 0	000BH
External INT1	0013H
Timer 1	001BH
Serial	0023H
Timer 2	002BH	Lowest

Interrupt Registers:

IE: Interrupt Enable (global and individual)
IP: Interrupt Priority

8.4. ARM Cortex-M NVIC (Nested Vectored Interrupt Controller)

Features:

Up to 240 interrupts
Configurable priority levels
Nested interrupt handling
Vector table in memory

9. Programming Examples

9.1. 8085 Assembly: Sum of Array

; Sum of 10 numbers stored from 2000H
        LXI H, 2000H   ; HL points to start of array
        MVI C, 10      ; Counter = 10
        XRA A          ; Clear accumulator (sum = 0)

LOOP:   ADD M          ; Add memory to accumulator
        INX H          ; Increment pointer
        DCR C          ; Decrement counter
        JNZ LOOP       ; Repeat if not zero

        STA 2100H      ; Store result
        HLT            ; Stop

9.2. 8051 C: Blink LED

#include <reg51.h>

sbit LED = P1^0;

void delay(unsigned int ms) {
    unsigned int i, j;
    for(i = 0; i < ms; i++)
        for(j = 0; j < 1275; j++);
}

void main() {
    while(1) {
        LED = 0;        // LED ON
        delay(500);     // Wait 500ms
        LED = 1;        // LED OFF
        delay(500);     // Wait 500ms
    }
}

9.3. 8051 Assembly: Timer Delay

; Generate 50ms delay using Timer 0 (Mode 1)
; Crystal = 11.0592MHz
; Machine cycle = 1.085μs
; Count = 50ms / 1.085μs = 46083
; Initial value = 65536 - 46083 = 19453 = 4BFDH

DELAY:  MOV TMOD, #01H  ; Timer 0, Mode 1
        MOV TH0, #4BH   ; Load high byte
        MOV TL0, #0FDH  ; Load low byte
        SETB TR0        ; Start timer
WAIT:   JNB TF0, WAIT   ; Wait for overflow
        CLR TR0         ; Stop timer
        CLR TF0         ; Clear flag
        RET

9.4. ARM Cortex-M (STM32) C: Blink LED

#include "stm32f4xx.h"

void delay(uint32_t count) {
    while(count--);
}

int main(void) {
    // Enable GPIOC clock
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
    
    // Configure PC13 as output
    GPIOC->MODER |= GPIO_MODER_MODER13_0;
    
    while(1) {
        GPIOC->BSRR = GPIO_BSRR_BS13;  // LED ON
        delay(500000);
        GPIOC->BSRR = GPIO_BSRR_BR13;  // LED OFF
        delay(500000);
    }
}

10. Summary Table: Microprocessor vs. Microcontroller

Feature	8085	8051	ARM Cortex-M
Architecture	CISC	CISC	RISC
Word size	8-bit	8-bit	32-bit
Clock speed	3-6 MHz	12-40 MHz	16-400 MHz
Internal RAM	0	128-256 bytes	4-512 KB
Internal ROM	0	4-64 KB	64 KB-2 MB
I/O pins	External	32	20-140
Timers	External	2-3	8-16
ADC	External	8-bit (optional)	12-bit (internal)
Power	High	Medium	Low
Applications	Education	Industrial, consumer	IoT, automotive, mobile

11. Key Equations Reference Sheet

Equation	Description
$2^{n}$	Memory addressing capability
$Delay = Count \times T_{cycle}$	Timer delay
$Initial = 2^{n} - Count$	Timer initial value
$Baud Rate = 32 2 ^{SMOD} \times 12 \times ( 256 - T H 1 ) f ^{osc}$	8051 baud rate
$T_{cycle} = f ^{osc} 12$	8051 machine cycle

12. Standard Textbooks

Author	Title	Focus
Gaonkar, R.S.	Microprocessor Architecture, Programming and Applications with 8085	8085-focused
Mazidi & Mazidi	The 8051 Microcontroller and Embedded Systems	8051-focused
Yiu, J.	The Definitive Guide to ARM Cortex-M3 and Cortex-M4	ARM-focused
Brey, B.B.	The Intel Microprocessors	x86-focused

13. Final Study Checklist

Topic	Key Skills
8085 Architecture	Identify registers; explain ALU, control unit
8085 Instructions	Write assembly programs; use addressing modes
Timing Diagrams	Draw opcode fetch, memory read/write cycles
8051 Architecture	Explain internal RAM, ROM, SFRs
8051 Peripherals	Program timers; use serial port; handle interrupts
ARM Cortex-M	Understand registers; write simple C programs
Memory Interfacing	Design address decoding; interface RAM/ROM
I/O Interfacing	Use 8255, 8254, 8259; program I/O ports
Interrupts	Configure interrupts; write ISRs

TE-152 Electronic Devices & Circuits – Detailed Study Notes

1. Introduction to Semiconductor Physics

1.1 Atomic Structure and Energy Bands

Aspect	Detail
Energy bands	Valence band (electrons bound to atoms), Conduction band (free electrons), Forbidden gap (no energy states)
Conductors	No forbidden gap (overlapping bands)
Semiconductors	Small forbidden gap (≈1.1 eV for Si, 0.7 eV for Ge)
Insulators	Large forbidden gap (>3 eV)

1.2 Intrinsic Semiconductors

Aspect	Detail
Definition	Pure semiconductor with no impurities
Carriers	Equal number of electrons and holes
Carrier concentration	nᵢ = pᵢ = BT^{3/2} e^{-E_g/2kT}
For Si at 300K	nᵢ ≈ 1.5 × 10¹⁰ cm⁻³

1.3 Extrinsic Semiconductors

Type	Doping	Majority Carriers	Minority Carriers	Donor/Acceptor Concentration
n-type	Pentavalent (P, As, Sb)	Electrons	Holes	N_D ≈ N_D⁺
p-type	Trivalent (B, Al, Ga)	Holes	Electrons	N_A ≈ N_A⁻

Mass Action Law:

n × p = nᵢ²

For n-type: n ≈ N_D, p ≈ nᵢ²/N_D

For p-type: p ≈ N_A, n ≈ nᵢ²/N_A

1.4 Carrier Transport Mechanisms

Mechanism	Description	Current Density
Drift	Movement due to electric field	J_drift = q(μ_n n + μ_p p)E
Diffusion	Movement due to concentration gradient	J_diff = qD_n (dn/dx) – qD_p (dp/dx)
Einstein relation	D/μ = kT/q (at room temperature ≈ 26 mV)

2. Semiconductor Diodes

2.1 p-n Junction Diode

Aspect	Detail
Structure	p-type and n-type semiconductor regions
Depletion region	Region devoid of free carriers, built-in potential
Built-in potential (V_bi)	V_bi = (kT/q) ln(N_A N_D / nᵢ²)

Biasing Conditions:

Biasing	Connection	Depletion Width	Current	Diode State
Forward bias	p (+), n (-)	Decreases	Large (exponential)	ON
Reverse bias	p (-), n (+)	Increases	Small (leakage)	OFF
Zero bias	No external voltage	Equilibrium	Zero	–

2.2 Diode V-I Characteristics

Shockley Diode Equation:

I_D = I_S (e^{V_D/(ηV_T)} - 1)

where:

I_S = reverse saturation current (typically 10⁻¹² to 10⁻⁶ A)
V_T = thermal voltage = kT/q ≈ 26 mV at 300K
η = ideality factor (≈1 for ideal, 1-2 for practical)

Cut-in Voltage (V_γ):

Silicon: 0.6 – 0.7 V
Germanium: 0.2 – 0.3 V
Schottky: 0.2 – 0.4 V

2.3 Diode Resistance

Resistance	Definition	Formula
DC (static) resistance	R_DC = V_D / I_D	–
AC (dynamic) resistance	r_d = dV_D/dI_D = ηV_T / I_D	~26 mV / I_D (mA)
Reverse resistance	R_R = V_R / I_R	Very large (MΩ)

2.4 Diode Capacitances

Type	Origin	Formula	Dominant Bias
Junction (depletion) capacitance	Charge variation in depletion region	C_j = C_{j0} / √(1 + V_R/V_bi)	Reverse bias
Diffusion capacitance	Charge storage in neutral regions	C_d = τ × (dI_D/dV_D) = τ × I_D/(ηV_T)	Forward bias

2.5 Diode Breakdown Mechanisms

Mechanism	Description	Temperature Coefficient	Occurs In
Zener breakdown	High electric field → tunneling	Negative	Heavily doped diodes (<5V)
Avalanche breakdown	Impact ionization	Positive	Lightly doped diodes (>6V)

2.6 Special Purpose Diodes

Diode Type	Symbol Feature	Characteristics	Applications
Zener diode	Bent line on cathode	Operates in reverse breakdown	Voltage regulation
Light Emitting Diode (LED)	Arrows pointing away	Emits light when forward biased	Indicators, displays
Photodiode	Arrows pointing toward	Light-sensitive reverse current	Light detection, sensors
Schottky diode	S-like symbol	Low forward voltage, fast switching	High-frequency circuits
Varactor (Varicap) diode	Capacitor-like symbol	Junction capacitance varies with voltage	Tuning circuits
Tunnel diode		Negative resistance region	High-frequency oscillators

2.7 Diode Applications

Rectifiers:

Type	Circuit	V_dc (avg)	PIV	Ripple Frequency	Efficiency
Half-wave	1 diode	V_m/π	V_m	f_in	40.6%
Full-wave (center-tapped)	2 diodes	2V_m/π	2V_m	2f_in	81.2%
Full-wave (bridge)	4 diodes	2V_m/π	V_m	2f_in	81.2%

Filters:

Filter	Components	Ripple Factor
Capacitor	C only	1/(2√3 f R_L C)
LC	L + C	√3/(2) × (X_C/X_L)
π (CLC)	C1 + L + C2	Very low

Clippers (Limiters):

Series positive clipper
Series negative clipper
Shunt positive clipper
Shunt negative clipper
Biased clippers

Clampers (DC Restorers):

Positive clamper
Negative clamper
Biased clampers

Voltage Multipliers:

Voltage doubler (half-wave, full-wave)
Voltage tripler
Voltage quadrupler

Zener Voltage Regulator:

V_out = V_Z
I_S = (V_in - V_Z)/R_S
I_Z = I_S - I_L
Condition: I_Z(min) < I_Z < I_Z(max)

3. Bipolar Junction Transistors (BJTs)

3.1 BJT Structure and Symbols

Type	Structure	Layers	Terminals	Arrow Direction
npn	n-p-n	Emitter (n), Base (p), Collector (n)	E, B, C	Emitter arrow out
pnp	p-n-p	Emitter (p), Base (n), Collector (p)	E, B, C	Emitter arrow in

3.2 BJT Modes of Operation

Mode	BE Junction	BC Junction	Applications
Cut-off	Reverse	Reverse	Switch OFF
Active (Forward active)	Forward	Reverse	Amplifier
Saturation	Forward	Forward	Switch ON
Reverse active	Reverse	Forward	Rarely used

3.3 BJT Current Relationships

I_E = I_B + I_C
I_C = β I_B   (DC current gain, typical 50-300)
I_C = α I_E   (α = β/(β+1) ≈ 1)
β = α/(1-α)
I_E = (β+1) I_B

3.4 BJT Configurations

Configuration	Input	Output	Current Gain	Voltage Gain	Input Z	Output Z	Phase Shift
Common Emitter (CE)	Base	Collector	High (β)	High	Medium	Medium	180°
Common Collector (CC)	Base	Emitter	High (β+1)	≈ 1	High	Low	0°
Common Base (CB)	Emitter	Collector	≈ 1	High	Low	High	0°

3.5 BJT Characteristics

Input (Base) Characteristics:

I_B vs. V_BE at constant V_CE
Similar to diode characteristic
V_BE ≈ 0.6-0.7 V (Si) in active region

Output (Collector) Characteristics:

I_C vs. V_CE at constant I_B
Three regions: cut-off, active, saturation
Early effect: I_C increases slightly with V_CE

Early Voltage (V_A):

Slope of I_C vs. V_CE in active region
I_C = I_S e^{V_BE/V_T} (1 + V_CE/V_A)

3.6 BJT Biasing Circuits

Biasing Method	Stability	Complexity	Applications
Fixed bias	Poor	Simple	Switching
Emitter bias	Fair	Simple	Basic amplifiers
Voltage divider bias	Excellent	Moderate	Most common
Collector feedback bias	Good	Moderate	Simple amplifiers

Voltage Divider Bias Design:

V_B = (R2/(R1+R2)) × V_CC
V_E = V_B - V_BE
I_E = V_E / R_E
I_C ≈ I_E
V_C = V_CC - I_C × R_C
V_CE = V_C - V_E

3.7 BJT as a Switch

State	V_BE	I_B	I_C	V_CE	Condition
Cut-off (OFF)	< 0.6 V	0	0	V_CC	V_in low
Saturation (ON)	≈ 0.7 V	≥ I_C/β	V_CC/R_C	≈ 0.2 V	V_in high

Design for Saturation:

I_C(sat) = V_CC / R_C
I_B(min) = I_C(sat) / β
R_B = (V_in - V_BE) / I_B (use I_B = 2-5× I_B(min) for hard saturation)

3.8 BJT Small-Signal Model (Hybrid-π)

Model Parameters:

g_m = I_C / V_T (transconductance)
r_π = β / g_m (base-emitter resistance)
r_o = V_A / I_C (output resistance, often neglected)
C_π = C_JE + τ_F × g_m (base-emitter capacitance)
C_μ = C_JC (base-collector capacitance)

Hybrid-π Equivalent Circuit:

Base  ──ww───┬───┬── Collector
            r_π   │
              │   │
              └───┼─── g_m·V_π ──┬─── r_o ──┐
                  │              │          │
                  └──────────────┴──────────┘
                 Emitter

3.9 BJT Amplifiers (Small-Signal Analysis)

Common Emitter Amplifier:

Voltage gain: A_v = -g_m (R_C || r_o)
Input impedance: Z_in = R1 || R2 || r_π
Output impedance: Z_out = R_C || r_o
Current gain: A_i = β

Common Collector (Emitter Follower):

Voltage gain: A_v ≈ 1
Input impedance: Z_in = R1 || R2 || (β+1)(R_E || R_L)
Output impedance: Z_out = R_E || (r_π/(β+1))

Common Base Amplifier:

Voltage gain: A_v = g_m (R_C || r_o)
Input impedance: Z_in = R_E || (r_π/(β+1))
Output impedance: Z_out = R_C || r_o
Current gain: A_i ≈ 1

4. Field Effect Transistors (FETs)

4.1 JFET (Junction Field Effect Transistor)

Aspect	Detail
Structure	n-channel or p-channel with gate-source junction
Terminals	Source (S), Gate (G), Drain (D)
Operation	Voltage-controlled device (V_GS controls channel resistance)
Shockley’s equation	I_D = I_DSS (1 – V_GS/V_P)²

JFET Regions:

Region	Condition	Application
Ohmic (Triode)	V_DS small, V_GS > V_P	Voltage-controlled resistor
Saturation (Pinch-off)	V_DS ≥ V_GS – V_P	Amplifier
Cut-off	V_GS ≤ V_P	Switch OFF

4.2 MOSFET (Metal Oxide Semiconductor FET)

Type	Enhancement Mode (normally off)	Depletion Mode (normally on)
n-channel	V_GS > V_TH to turn on	V_GS < 0 to turn off
p-channel	V_GS < V_TH to turn on	V_GS > 0 to turn off

MOSFET Regions:

Region	Condition	Application
Cut-off	V_GS < V_TH	Switch OFF
Triode (Ohmic)	V_GS > V_TH, V_DS < V_GS – V_TH	Voltage-controlled resistor
Saturation	V_GS > V_TH, V_DS ≥ V_GS – V_TH	Amplifier

MOSFET Equations:

Triode region: I_D = K [2(V_GS – V_TH)V_DS – V_DS²]
Saturation region: I_D = K (V_GS – V_TH)² (where K = (1/2)μ_n C_ox (W/L))

4.3 FET vs. BJT Comparison

Parameter	BJT	JFET	MOSFET
Control	Current-controlled (I_B)	Voltage-controlled (V_GS)	Voltage-controlled (V_GS)
Input impedance	Low (1-5 kΩ)	High (MΩ)	Very high (10⁹-10¹⁵ Ω)
Gain	High (β=50-300)	Low (g_m=1-10 mS)	Low to moderate
Noise	Moderate	Low	Low
Temperature stability	Poor	Good	Good
Switching speed	Moderate	Slow	Fast
Fabrication	Bipolar	JFET process	CMOS

4.4 FET Biasing

Biasing Method	Application
Fixed bias	Simple, poor stability
Self-bias	Common for JFETs
Voltage divider bias	Most stable
Current source bias	Best stability (ICs)

JFET Self-Bias:

V_GS = -I_D R_S
I_D = I_DSS (1 - V_GS/V_P)²
Solve for I_D and V_GS

4.5 FET Small-Signal Model

Parameters:

g_m = ∂I_D/∂V_GS = (2I_DSS/|V_P|)(1 - V_GS/V_P) = (2I_D)/|V_GS - V_P|
r_d = ∂V_DS/∂I_D = V_A/I_D (output resistance)

Small-Signal Equivalent Circuit:

Gate ──────┬───┬── Drain
           │   │
           │   └─── g_m·V_GS ──┬─── r_d ──┐
           │                  │          │
           └──────────────────┴──────────┘
          Source

4.6 FET Amplifiers

Configuration	Voltage Gain	Input Impedance	Output Impedance
Common Source (CS)	-g_m(R_D		r_d)	Very high	R_D	r_d
Common Drain (CD)	≈ 1	Very high	1/g_m		R_S
Common Gate (CG)	g_m(R_D		r_d)	1/g_m	R_D	r_d

5. Multistage Amplifiers

5.1 Coupling Methods

Method	Frequency Response	Advantages	Disadvantages
RC coupling	Bandpass (blocks DC)	Simple, cheap	Low frequency cut-off
Direct coupling	DC to high frequency	Good for ICs	DC drift
Transformer coupling	Bandpass	Impedance matching	Expensive, bulky

5.2 Cascade Amplifier Gain

A_v(total) = A_v1 × A_v2 × A_v3 × ...

5.3 Darlington Pair

Aspect	Detail
Configuration	Two BJTs connected with collectors common, emitter of first to base of second
Current gain	β_D = β₁ × β₂ (very high)
Input impedance	Z_in ≈ β₁ × β₂ × R_E (very high)
Output impedance	Low
Applications	Buffers, high-gain stages

6. Power Amplifiers

6.1 Classification by Conduction Angle

Class	Conduction Angle	Efficiency	Distortion	Applications
A	360°	25% (max)	Low	Small-signal, low power
B	180°	78.5%	Moderate	Push-pull audio
AB	180-360°	50-70%	Low	High-fidelity audio
C	<180°	>80%	High	RF amplifiers
D	Switching	>90%	Low (filtered)	Digital audio

6.2 Class A Amplifier

Single-ended:

Q-point at center of load line
Maximum efficiency = 25%
Output power = I_CQ² × R_L / 2

6.3 Class B Push-Pull Amplifier

Aspect	Detail
Configuration	Two complementary transistors (npn and pnp)
Operation	Each conducts for 180°
Crossover distortion	Occurs near zero crossing
Maximum efficiency	78.5%
Output power	V_CC²/(2R_L) (peak)

6.4 Class AB Amplifier

Biased slightly above cut-off to eliminate crossover distortion
Compromise between efficiency and distortion

6.5 Heat Sinks and Power Dissipation

Thermal Resistance:

θ_JA = θ_JC + θ_CS + θ_SA
T_J = T_A + P_D × θ_JA
where:
θ_JC = junction-to-case, θ_CS = case-to-sink, θ_SA = sink-to-ambient

7. Sample Exam Questions

Short Answer (5 marks each)

Distinguish between intrinsic and extrinsic semiconductors. Explain doping.
Draw and explain the V-I characteristics of a p-n junction diode. Mark the cut-in voltage and breakdown voltage.
Explain the three regions of operation of a BJT.
Distinguish between BJT and MOSFET.
What are the advantages of Class B push-pull amplifier over Class A?

Numerical Problems (10-15 marks)

1. Diode Circuit:
For the circuit shown, find I_D and V_D. Assume Si diode (V_γ=0.7V), V_CC=10V, R=1kΩ.

Solution:

Assuming diode is forward biased:
V_D = 0.7 V
I_D = (V_CC - V_D)/R = (10 - 0.7)/1000 = 9.3 mA
Check: I_D > 0, assumption correct.

2. BJT Biasing:
For the voltage divider bias circuit: V_CC=12V, R1=47kΩ, R2=10kΩ, R_C=2.2kΩ, R_E=1kΩ, β=100. Find V_B, V_E, I_C, V_C, V_CE.

Solution:

V_B = (R2/(R1+R2)) × V_CC = (10/57) × 12 = 2.105 V
V_E = V_B - V_BE = 2.105 - 0.7 = 1.405 V
I_E = V_E/R_E = 1.405/1000 = 1.405 mA
I_C ≈ I_E = 1.405 mA
V_C = V_CC - I_C×R_C = 12 - 1.405×2.2 = 12 - 3.091 = 8.909 V
V_CE = V_C - V_E = 8.909 - 1.405 = 7.504 V

3. CE Amplifier Gain:
For the CE amplifier above, find voltage gain A_v = v_out/v_in. Assume r_o = ∞, V_T=26mV.

Solution:

r_e = V_T/I_E = 26/1.405 = 18.5 Ω
A_v = -R_C/r_e = -2200/18.5 = -119

4. Class A Amplifier Power:
A Class A amplifier has V_CC=12V, I_CQ=100mA, R_L=100Ω. Find output power, input power, and efficiency.

Solution:

V_CEQ = V_CC/2 = 6V (for maximum swing)
P_out(max) = I_CQ² × R_L/2 = (0.1)² × 100/2 = 0.5 W
P_in = V_CC × I_CQ = 12 × 0.1 = 1.2 W
η = P_out/P_in = 0.5/1.2 = 41.7%
(Note: theoretical max for Class A is 25% when R_L is transformer coupled)

Quick Revision Table – Diode Parameters

Parameter	Silicon	Germanium	Schottky
Cut-in voltage	0.6-0.7 V	0.2-0.3 V	0.2-0.4 V
Reverse leakage	nA-μA	μA	μA-mA
Reverse recovery time	μs-ns	μs	ns
Max temperature	150-200°C	75-100°C	125-150°C

Quick Revision Table – BJT Configurations

Parameter	CE	CC	CB
Voltage gain	High	≈1	High
Current gain	High (β)	High (β+1)	≈1
Input impedance	Medium	High	Low
Output impedance	Medium	Low	High
Phase shift	180°	0°	0°

Quick Revision Table – FET Configurations

Parameter	CS	CD	CG
Voltage gain	High	≈1	High
Current gain	High	High	≈1
Input impedance	Very high	Very high	Low
Output impedance	Medium	Low	High
Phase shift	180°	0°	0°

TE-248: Computer Communication Networks – Comprehensive Study Notes

These notes provide a complete framework for Computer Communication Networks, covering the fundamental principles of how data moves between computers, the layered architecture of network protocols, physical media, and key protocols at each layer. The focus is on understanding the “how” and “why” of network communication, from the physical transmission of bits to the end-user applications we interact with daily.

Part 1: Foundations of Networking

1.1 What is a Computer Network?

A computer network is a collection of autonomous computers connected together to share resources and exchange information. The key word is “autonomous”—each computer is independent and self-governing, unlike a distributed system where multiple computers work together as a single unit .

Main Purposes of Networking:

Resource sharing: Printers, storage, applications
Communication: Email, messaging, video calls
Data access: Centralized databases, file servers
Reliability: Redundant systems and backup

1.2 Computer Network vs. Distributed System

Aspect	Computer Network	Distributed System
User awareness	Users know about multiple computers	Users see a single unified system
Control	Each computer operates independently	Centralized control through middleware
Failure impact	One computer failure doesn’t affect others	Partial failure may affect entire system
Primary use	Resource sharing	Processing large tasks in parallel

A distributed system is built on top of a network, with additional software (middleware) that makes multiple computers appear as a single system to users .

1.3 Classifications by Scale

Network Type	Geographical Scope	Characteristics	Examples
LAN (Local Area Network)	Room, building, campus	Privately owned, high speed, low error rate	Home Wi-Fi, office Ethernet
MAN (Metropolitan Area Network)	City-wide	Covers area larger than LAN, smaller than WAN	Cable TV network, city Wi-Fi
WAN (Wide Area Network)	Country, continent, global	Spans large geographical areas, uses routers	The Internet, corporate networks

A key distinction for LANs is that all nodes share the same broadcast domain and physical medium .

1.4 Network Topologies

Topology is the “shape” of the connections—how devices are physically or logically arranged .

Physical Topologies

Topology	Description	Advantages	Disadvantages
Bus	Single cable connects all nodes	Simple, inexpensive, easy to extend	Single point of failure (the bus), limited length
Ring	Each node connects to two others forming a circle	Deterministic access (token-based), good under heavy load	Single node failure can break entire ring
Star	All nodes connect to central hub/switch	Easy to add nodes, fault isolation (single node failure doesn’t affect others)	Central device is single point of failure
Mesh	Every node connects to every other (full mesh) or many nodes (partial mesh)	High redundancy, multiple paths for data	Expensive, complex wiring
Tree	Hierarchical combination of star topologies on a bus	Scalable, flexible	Complex configuration

Performance Characteristics :

Bus topology: Excellent under low load (few collisions), degrades under high load
Ring topology: Deterministic (stations can predict when they’ll get access), good under heavy load
Star topology: Single node failure doesn’t affect others; central hub is critical
Mesh topology: Highest reliability but highest cost

1.5 Evolution of Computer Networks

Era	Development	Significance
1950s-1960s	Time-sharing, batch processing	Terminals connected directly to mainframes
1964	Paul Baran’s packet network reports	Foundation for packet-switching concept
1969	ARPANET becomes operational	First true packet-switched network
1972	First email system (Ray Tomlinson)	Killer application for networking
1980	TCP/IP becomes operational	Standard protocol suite adopted
1983	ARPANET fully adopts TCP/IP	Birth of modern Internet
1990	ARPANET retired	End of original network
1991	World Wide Web developed	Made the Internet accessible to the public

The invention of email actually predates TCP/IP—the first email system was developed in 1972, eight years before TCP/IP became operational .

Part 2: The OSI and TCP/IP Models

2.1 Why Layered Models?

Networking is complex. To manage this complexity, designers use a layered approach (divide and conquer) where each layer handles a specific part of the communication problem .

Benefits of Layering :

Independence: Each layer can be developed and changed separately
Flexibility: Different implementations can provide the same service
Standardization: Clear interfaces enable interoperability between vendors
Simplification: Complex problems broken into manageable pieces

2.2 The OSI 7-Layer Model

The Open Systems Interconnection (OSI) model is a conceptual framework developed by ISO to standardize network communication .

Layer	Name	Function	PDU (Protocol Data Unit)
7	Application	User interface, application services	Data
6	Presentation	Data formatting, encryption, compression	Data
5	Session	Connection management, synchronization	Data
4	Transport	End-to-end reliability, segmentation	Segment
3	Network	Routing, logical addressing (IP)	Packet
2	Data Link	Physical addressing (MAC), error detection	Frame
1	Physical	Bit transmission over media	Bits

Mnemonic to remember the order (top to bottom) :

All People Seem To Need Data Processing

2.3 The TCP/IP Model

The TCP/IP model is the practical model used for the Internet. It has four layers :

Layer	OSI Equivalent	Function	Key Protocols
Application	Layers 5-7	User applications, data exchange	HTTP, FTP, SMTP, DNS, Telnet
Transport	Layer 4	End-to-end connections, reliability	TCP, UDP
Internet	Layer 3	Routing, logical addressing	IP, ICMP, ARP
Network Access	Layers 1-2	Physical transmission, framing	Ethernet, Wi-Fi, PPP

2.4 OSI vs. TCP/IP Comparison

Aspect	OSI Model	TCP/IP Model
Number of layers	7	4
Status	Theoretical standard	Practical/industrial standard
Protocols	Defines services, not specific protocols	Specifies actual protocols
Usage	Teaching, documentation, troubleshooting	The actual Internet
Adoption	Widely referenced but not fully implemented	Universal

A helpful guideline: “When discussing layers of a model, we are usually referring to the OSI model. When discussing protocols, we are usually referring to the TCP/IP model” .

2.5 Encapsulation and PDU Flow

Encapsulation is the process where each layer adds its own header (and sometimes trailer) to the data as it passes down the protocol stack .

Application Data (ADU)
      │
      ▼
Transport Layer: Adds TCP/UDP header → Segment (TCP) or Datagram (UDP)
      │
      ▼
Network Layer: Adds IP header → Packet
      │
      ▼
Data Link Layer: Adds Ethernet header and trailer → Frame
      │
      ▼
Physical Layer: Transmits bits

Encapsulation Example (TCP/IP over Ethernet) :

TCP header: 20 bytes minimum
IP header: 20 bytes for IPv4
Ethernet header: 14 bytes
Ethernet trailer: 4 bytes
Preamble + SFD: 8 bytes

Overhead calculation: 66 bytes overhead. For a 1500-byte data payload, overhead is about 4.2%. For 100 bytes of data, overhead jumps to nearly 40%.

Part 3: Physical Layer

3.1 Guided Media (Wired)

Medium	Characteristics	Speed/Distance	Typical Use
Twisted Pair (UTP/STP)	Inexpensive, flexible, susceptible to interference	Cat5e: 1 Gbps/100m; Cat6: 10 Gbps/100m	Ethernet LANs, telephone
Coaxial Cable	Better shielding than twisted pair, higher bandwidth	10 Mbps/500m (10Base5), 100 Mbps/185m (10Base2)	Cable TV, older Ethernet
Fiber Optic	High speed, immune to EMI, long distance, expensive	1-100 Gbps/km to 100+ km	Backbone, long-haul, data centers

UTP Categories :

Cat 3: 10 Mbps Ethernet (10BaseT)
Cat 5e: 1 Gbps Ethernet (1000BaseT)
Cat 6: 10 Gbps Ethernet (10GBASE-T) up to ~100 meters
Cat 6a: 10 Gbps Ethernet at 100 meters

Fiber Types :

Type	Wavelength	Core Diameter	Range	Color
Multimode (850 nm)	850 nm (sometimes 1310 nm)	50 or 62.5 μm	<2 km (100 Mbps), <300 m (1 Gbps)	Orange
Single-mode (1310 nm)	1310 nm or 1550 nm	8-10 μm	1-70+ km	Yellow

Connectors: SC, ST, LC (fiber); RJ45 (twisted pair); BNC (coaxial) .

3.2 Unguided Media (Wireless)

Medium	Frequency Range	Range	Characteristics
Radio	Varies (3 kHz-300 GHz)	Varies	Omnidirectional, passes through walls
Microwave	1-300 GHz	Line-of-sight, miles	High bandwidth, requires clear path
Satellite	1-50 GHz	Global	Covers large areas, high latency
Infrared	~300 GHz-400 THz	Short, line-of-sight	Low cost, cannot penetrate walls

3.3 Older Ethernet Physical Standards

Standard	Cable	Topology	Segment Length	Speed
10Base5 (ThickNet)	Thick coaxial	Bus	500 m	10 Mbps
10Base2 (ThinNet)	Thin coaxial (RG58)	Bus	185 m	10 Mbps
10BaseT	Cat 3 UTP	Star (hub)	100 m	10 Mbps
10BaseFL	Multimode fiber	Star	2 km	10 Mbps

3.4 Modern Ethernet Standards

Standard	Media	Segment Length	Speed
100BaseTX	Cat 5e UTP (2 pairs)	100 m	100 Mbps
1000BaseT	Cat 5e UTP (4 pairs)	100 m	1 Gbps
1000BaseSX	Multimode fiber (850 nm)	220-500 m	1 Gbps
1000BaseLX	Single-mode fiber (1310 nm)	5 km+	1 Gbps
10GBASE-T	Cat 6/6a UTP	55-100 m	10 Gbps
10GBASE-SR	Multimode fiber (850 nm)	80-300 m	10 Gbps
10GBASE-LR	Single-mode fiber (1310 nm)	10-25 km	10 Gbps

Part 4: Data Link Layer (Layer 2)

4.1 Functions of the Data Link Layer

The data link layer sits between the physical layer and the network layer, providing reliable data transfer across a single physical link .

Function	Description
Framing	Breaks bit stream into manageable frames, marks frame boundaries
Error Control	Detects and optionally corrects transmission errors
Flow Control	Prevents fast sender from overwhelming slow receiver
Medium Access Control (MAC)	Determines which device can transmit when (shared media)
Physical Addressing	Uses MAC addresses to identify devices on the same network

4.2 Framing

The data link layer receives a raw bit stream from the physical layer and must detect where frames begin and end. Common framing methods include:

Character count: Header includes frame length (vulnerable to errors)
Byte stuffing: Special flag bytes mark boundaries, with escape characters for data containing flags
Bit stuffing: Flag bit pattern (01111110) with zero insertion after five consecutive 1s
Physical layer coding violations: Using invalid signal patterns as delimiters

4.3 Error Detection

Errors occur during transmission due to noise, interference, or signal degradation. Error detection codes allow the receiver to determine if data was corrupted .

Parity Check:

Even parity: Total number of 1s (including parity bit) is even
Odd parity: Total number of 1s is odd
Detects single-bit errors but not even numbers of bit errors

Checksum:

Simple algorithm that calculates binary values in a packet
Receiver computes new checksum and compares with transmitted checksum

Cyclic Redundancy Check (CRC) :

Most powerful and widely used error detection method
Treats bit string as polynomial; divides by generator polynomial
Can detect all single-bit errors, most double-bit errors, and burst errors up to the polynomial degree
Used in Ethernet, Wi-Fi, and many other standards

4.4 Flow Control

Flow control prevents a fast sender from overwhelming a slow receiver .

Stop-and-Wait:

Sender sends one frame, waits for acknowledgment, then sends next
Simple but inefficient (link idle during waiting period)

Sliding Window:

Sender can transmit multiple frames before receiving acknowledgment
Window size: Number of outstanding (unacknowledged) frames allowed
Go-Back-N: On error, retransmits from the lost frame onward
Selective Repeat: Retransmits only the lost frames (more efficient but more complex)

4.5 Medium Access Control (MAC)

When multiple devices share the same physical medium, a MAC protocol determines who can transmit when .

Random Access Protocols:

CSMA/CD (Carrier Sense Multiple Access with Collision Detection): Listen before transmitting; if collision detected, stop and retry after random delay. Used in classic Ethernet.
CSMA/CA (Collision Avoidance): Used in Wi-Fi (wireless networks cannot detect collisions effectively)

Controlled Access Protocols:

Token Passing: A special “token” circulates; only the token holder can transmit. Used in Token Ring and FDDI.
Polling: A central controller invites stations to transmit.

4.6 Data Link Layer Devices

Device	Layer	Function
Bridge	Data Link	Connects two network segments; forwards frames based on MAC address
Switch	Data Link	Multi-port bridge; learns MAC addresses; forwards frames only to destination port
Network Interface Card (NIC)	Data Link + Physical	Provides physical connection to network; has unique MAC address

Part 5: Network Layer (Layer 3)

5.1 Functions of the Network Layer

The network layer handles the routing of packets across multiple networks from source to destination.

Function	Description
Logical Addressing	Assigns IP addresses that identify devices globally
Routing	Determines the best path for packets through the network
Packet Forwarding	Moves packets from router to router toward destination
Fragmentation/Reassembly	Breaks large packets into smaller ones for networks with smaller MTU

5.2 Internet Protocol (IP)

IPv4:

32-bit addresses (e.g., 192.168.1.1)
Approximately 4.3 billion possible addresses
Address exhaustion led to development of IPv6

IPv6:

128-bit addresses
Virtually unlimited addresses
Includes built-in security (IPsec) and simplified header

IP Packet Header (IPv4):

Source and destination IP addresses
Time-to-Live (TTL) prevents infinite looping
Protocol field (TCP = 6, UDP = 17)
Checksum for header error detection
Fragmentation fields

5.3 Routing Protocols

Protocol	Type	Algorithm	Characteristics
RIP (Routing Information Protocol)	Distance Vector	Bellman-Ford	Simple, limited to 15 hops
OSPF (Open Shortest Path First)	Link State	Dijkstra	Faster convergence, hierarchical design
BGP (Border Gateway Protocol)	Path Vector	Policy-based	Used between autonomous systems (the Internet backbone)

5.4 Network Layer Devices

Device	Layer	Function
Router	Network	Connects different networks; routes packets based on IP addresses; separates broadcast domains
Layer 3 Switch	Network	Switch with routing capabilities
Gateway	Various	Connects networks with different protocols

Part 6: Transport Layer (Layer 4)

6.1 Functions of the Transport Layer

The transport layer provides logical communication between application processes running on different hosts .

Function	Description
Multiplexing/Demultiplexing	Uses port numbers to direct data to the correct application
Segmentation	Breaks application data into manageable segments
Reliability (TCP)	Provides acknowledgments, retransmissions, error recovery
Flow Control (TCP)	Prevents sender from overwhelming receiver
Congestion Control (TCP)	Prevents sender from overwhelming the network

6.2 TCP vs. UDP Comparison

Feature	TCP	UDP
Connection type	Connection-oriented	Connectionless
Reliability	Reliable (acknowledgments, retransmission)	Unreliable (no acknowledgments)
Ordering	Preserves packet order	No ordering guarantee
Flow control	Yes (window-based)	No
Congestion control	Yes	No
Error checking	Yes	Yes (optional checksum)
Header size	20 bytes (minimum)	8 bytes
Speed	Slower (overhead)	Faster
Best for	Web, email, file transfer, SSH	Streaming, VoIP, gaming, DNS

TCP guarantees delivery—if data is lost during transmission, TCP detects the loss and retransmits the missing data. The application layer (e.g., HTTP) does not get involved in error recovery .

6.3 Port Numbers

Port numbers allow multiple applications to use the network simultaneously on the same host. The combination of IP address + port number is called a socket .

Port Range	Type	Use
0-1023	Well-known ports	System services, assigned by IANA
1024-49151	Registered ports	User applications, registered with IANA
49152-65535	Dynamic/Private	Temporary, assigned by OS

Common Well-Known Ports :

Port	Protocol	Service
20,21	FTP	File Transfer Protocol
22	SSH	Secure Shell
23	Telnet	Remote terminal
25	SMTP	Email sending
53	DNS	Domain Name System
80	HTTP	Web (unsecured)
110	POP3	Email retrieval
143	IMAP	Email retrieval (advanced)
443	HTTPS	Secure web
3389	RDP	Remote Desktop

6.4 TCP Reliability Mechanisms

Error Recovery (Positive Acknowledgment with Retransmission – PAR) :

Sender transmits data and starts a timer
Receiver sends acknowledgment (ACK) for successfully received data
If sender doesn’t receive ACK before timer expires, it retransmits

The sequence number field in the TCP header tracks every byte of data, allowing the receiver to detect missing segments and the sender to know which data has been acknowledged .

Flow Control (Windowing) :

The receiver advertises a window size indicating how much data it can accept
Sender cannot transmit more than the window size without receiving an acknowledgment
Window size is negotiated during connection establishment and can change dynamically

6.5 TCP Connection Management

Three-Way Handshake (Connection Establishment) :

Client sends SYN (synchronize) packet with initial sequence number
Server responds with SYN-ACK (synchronize-acknowledge)
Client sends ACK to confirm

Four-Way Termination:

Sender sends FIN (finish) to close connection
Receiver acknowledges with ACK
Receiver sends its own FIN
Sender acknowledges with ACK

The SYN and ACK flags are 1-bit fields in the TCP header used to signal connection management operations .

Part 7: Application Layer (Layer 7)

7.1 Client-Server Model

The most common model for network applications :

Client: Initiates communication, sends requests
Server: Waits for requests, sends responses
Servers can handle multiple clients simultaneously
Examples: Web browsing (browser = client, web server = server)

7.2 Common Application Layer Protocols

Protocol	Port	Purpose	Characteristics
HTTP/HTTPS	80/443	Web page transfer	Stateless; HTTPS adds encryption (SSL/TLS)
FTP	20,21	File transfer	Uses separate control (21) and data (20) connections
SMTP	25	Sending email	Used by email clients to send mail to servers
POP3	110	Retrieving email	Downloads email to client, removes from server
IMAP	143	Retrieving email	Keeps email on server, allows folder management
DNS	53	Domain name resolution	Converts domain names (google.com) to IP addresses
Telnet	23	Remote terminal	Unencrypted (legacy, use SSH instead)
SSH	22	Secure remote terminal	Encrypted, also supports file transfer (SFTP)
DHCP	67,68	IP address assignment	Automatically configures network settings
SNMP	161	Network management	Monitors network devices

7.3 DNS (Domain Name System)

DNS is often called the “phonebook of the Internet”—it translates human-readable domain names (www.example.com) into machine-readable IP addresses (93.184.216.34) .

DNS Hierarchy:

Root Domain
    └── .com, .org, .edu (Top-Level Domains)
            └── example.com (Second-Level Domain)
                    └── www.example.com (Subdomain)

Resolution Process:

Browser checks local cache
Query DNS resolver (usually ISP)
Resolver queries root nameserver
Root points to TLD nameserver (.com)
TLD points to authoritative nameserver (example.com)
Authoritative server returns IP address

Part 8: Network Devices Summary

Device	Layer	Function	Key Characteristics
NIC	1,2	Connects device to network	Has unique MAC address
Repeater	1	Regenerates signal to extend distance	Works at bit level, no intelligence
Hub	1	Multi-port repeater	Broadcasts all data to all ports; collisions common
Bridge	2	Connects two network segments	Forwards based on MAC address; learns which devices are on each side
Switch	2	Multi-port bridge	Forwards only to destination port; learns MAC addresses; reduces collisions
Router	3	Connects different networks	Routes based on IP address; separates broadcast domains; connects LAN to WAN
Gateway	Various	Connects networks with different protocols	Translates between different network technologies
Modem	1	Modulates/demodulates signals	Converts digital to analog for phone/cable lines

Part 9: Network Security Fundamentals

9.1 Basic Security Concepts

Term	Definition
Authorization	Determining what resources a user can access
Authentication	Verifying user identity (password, biometrics)
Firewall	Filters traffic between networks based on rules
Encryption	Scrambling data to prevent unauthorized reading
VPN (Virtual Private Network)	Creates encrypted tunnel over public network

9.2 Common Network Threats

Threat	Description
Eavesdropping	Passive listening to network traffic
Man-in-the-Middle	Attacker intercepts and possibly alters communication
Denial of Service (DoS)	Overwhelming target with traffic to make it unavailable
IP Spoofing	Forging source IP address to impersonate another system

Part 10: Key Formulas Summary

Concept	Formula/Value
CRC	Polynomial division for error detection
TCP Header	20 bytes minimum
IPv4 Header	20 bytes minimum (no options)
Ethernet MTU	1500 bytes
Well-known ports	0-1023
Registered ports	1024-49151
Dynamic ports	49152-65535
MAC address length	48 bits (6 bytes)
IPv4 address length	32 bits (4 bytes)
IPv6 address length	128 bits (16 bytes)
Ethernet frame overhead	14 bytes header + 4 bytes trailer (+8 bytes preamble)

Part 11: Study Tips for TE-248

Master the layered models (OSI and TCP/IP) – Know the layers, their order, and the function of each layer. This is the framework for everything else.
Understand encapsulation – Be able to describe how data changes as it moves down the stack. Know the PDU names (segment, packet, frame).
Memorize key port numbers – HTTP (80), HTTPS (443), FTP (21), SSH (22), SMTP (25), DNS (53), POP3 (110).
Distinguish between TCP and UDP – Know the differences: reliability, connection-oriented vs. connectionless, flow control, header size, typical applications.
Learn common network devices – Switch (Layer 2) vs. Router (Layer 3) vs. Hub (Layer 1) vs. Gateway.
Practice subnetting – If covered in your course, practice converting between binary and decimal, calculating network addresses, broadcast addresses, and usable host ranges.
Use mnemonic devices – Remember OSI layers with “All People Seem To Need Data Processing.”
Connect to real applications – When using the internet, think about which protocols are at work (DNS lookup, HTTP request, TCP connection, Ethernet framing).
Check units – Data rates in bits per second (bps), file sizes in bytes (B). 1 byte = 8 bits.
Use the search results – The syllabi and study guides provide clear outlines of core topics: network models, devices, topologies, protocols, and application layer services .

Part 12: Recommended Resources

Resource	Focus
Computer Networking: A Top-Down Approach – Kurose & Ross	Application-oriented approach
Computer Networks – Tanenbaum & Wetherall	Comprehensive reference
Beej’s Guide to Network Programming	Socket programming tutorials
Wireshark (free tool)	Packet capture and analysis
IETF RFCs	Protocol specifications (official standards)

These notes provide a comprehensive framework for TE-248: Computer Communication Networks. Success requires understanding the layered architecture (OSI and TCP/IP models), mastering key protocols (TCP, UDP, IP, HTTP, DNS), knowing network devices and topologies, and applying error detection and flow control concepts. Computer networks are the foundation of the Internet, cloud computing, and virtually all modern communication systems—essential knowledge for any computer science or IT professional.

TE-364: Wireless & Mobile Communication

Here are detailed study notes for TE-364: Wireless & Mobile Communication, written from an Electrical/Telecommunication Engineering perspective. These notes cover the fundamental principles of wireless and mobile communication systems—cellular concepts, radio propagation, modulation techniques, multiple access methods, diversity techniques, and wireless standards. The emphasis is on understanding how voice and data are transmitted over wireless channels and how mobile networks are designed.

1. Introduction to Wireless Communication

1.1. What is Wireless Communication?

Wireless Communication is the transfer of information between two or more points without the use of electrical conductors or wires. It uses electromagnetic waves to carry signals through free space.

The Core Question: How do we reliably transmit and receive information over radio channels that are subject to fading, interference, and noise?

1.2. Advantages and Disadvantages of Wireless

Advantages	Disadvantages
Mobility	Limited bandwidth
Rapid deployment	Interference
Lower infrastructure cost	Security concerns
Accessibility in remote areas	Signal propagation issues
Flexibility	Power consumption

1.3. Historical Development

Year	Development
1895	Marconi demonstrates wireless telegraphy
1906	First voice transmission (Reginald Fessenden)
1946	First commercial mobile telephone service (St. Louis)
1979	First 1G cellular system (NTT, Japan)
1981	Nordic Mobile Telephone (NMT) – 1G analog
1991	GSM introduced (2G digital)
2001	First 3G commercial launch (Japan)
2009	First 4G LTE commercial launch
2019	First 5G commercial launch

1.4. Wireless Generations

Generation	Technology	Data Rate	Features
1G	Analog (AMPS, NMT, TACS)	< 2.4 kbps	Voice only
2G	Digital (GSM, CDMA, TDMA)	9.6-14.4 kbps	Voice, SMS
2.5G	GPRS, EDGE	50-200 kbps	Basic data
3G	UMTS (WCDMA), CDMA2000	384 kbps – 2 Mbps	Voice, data, video
3.5G	HSPA, HSPA+	7.2-42 Mbps	Mobile broadband
4G	LTE, LTE-Advanced	100 Mbps – 1 Gbps	Full IP, high-speed data
5G	NR (New Radio)	1-20 Gbps	eMBB, URLLC, mMTC
6G	(Under development)	> 100 Gbps	Terahertz, AI-integrated

2. Cellular Concepts

2.1. Cellular System Architecture

┌─────────────────────────────────────────────────────────────┐
│                      Cellular Network                        │
│                                                              │
│                    ┌─────────────┐                          │
│                    │    MSC      │                          │
│                    │(Mobile Switching│                        │
│                    │   Center)   │                          │
│                    └──────┬──────┘                          │
│                           │                                 │
│         ┌─────────────────┼─────────────────┐               │
│         │                 │                 │               │
│    ┌────▼────┐       ┌────▼────┐       ┌────▼────┐          │
│    │   BSC   │       │   BSC   │       │   BSC   │          │
│    └────┬────┘       └────┬────┘       └────┬────┘          │
│         │                 │                 │               │
│    ┌────┴────┐       ┌────┴────┐       ┌────┴────┐          │
│    │   BTS   │       │   BTS   │       │   BTS   │          │
│    └─────────┘       └─────────┘       └─────────┘          │
│                                                              │
│    Mobile Station (MS)                                      │
└─────────────────────────────────────────────────────────────┘

Component	Function
MS (Mobile Station)	User device (handset)
BTS (Base Transceiver Station)	Radio interface, covers one cell
BSC (Base Station Controller)	Manages multiple BTSs, handover
MSC (Mobile Switching Center)	Call routing, switching, billing
HLR (Home Location Register)	Permanent subscriber database
VLR (Visitor Location Register)	Temporary subscriber data for roaming

2.2. Cell Geometry

Hexagonal cells are used for efficient coverage.

       /\
    /      \
   /    /\   \
  /   /    \   \
  \   \    /   /
   \    \/    /
    \      /
       \/

Cell parameters:

Radius (R): distance from center to vertex
Interference distance (D): distance between co-channel cells

2.3. Frequency Reuse

Frequency reuse factor (N):

$N = i^{2} + ij + j^{2}$

Where i, j are integers.

Common reuse patterns:

N	i, j	Description
1	1,0	No reuse (single frequency)
3	1,1	3-cell pattern
4	2,0	4-cell pattern
7	2,1	7-cell pattern (most common)
12	3,1	12-cell pattern

Co-channel reuse ratio:

$Q = R D = 3 N$

2.4. Cell Capacity

Number of channels per cell:

$k = N S$

Where:

S = total number of available channels
N = reuse factor

Erlang B formula (blocking probability):

$P_{b} = \sum ^{k = 0 C} A ^{k} / k ! A ^{C} / C !$

Where:

A = offered traffic (Erlangs)
C = number of channels

Traffic intensity (Erlang):

$A = λ \times T$

Where:

λ = call arrival rate (calls/hour)
T = average call duration (hours)

2.5. Cell Splitting and Sectoring

Cell Splitting: Dividing a congested cell into smaller cells to increase capacity.

Sectoring: Using directional antennas to divide a cell into sectors (3, 4, or 6 sectors).

Capacity improvement with sectoring:

$Capacity gain = Number of sectors$

2.6. Handover (Handoff)

Handover is the process of transferring an active call from one cell to another.

Type	Description
Intra-BSC	Between BTSs under same BSC
Inter-BSC	Between BSC under same MSC
Inter-MSC	Between different MSCs
Hard Handover	Break before make (GSM)
Soft Handover	Make before break (CDMA)
Softer Handover	Between sectors of same BTS

Handover margin:

$HO Margin = P_{current} - P_{target}$

3. Radio Propagation

3.1. Propagation Mechanisms

Mechanism	Description
Reflection	Wave bounces off large surfaces (ground, buildings)
Diffraction	Wave bends around obstacles (shadowing)
Scattering	Wave scatters from rough surfaces
Refraction	Wave bends due to atmospheric changes

3.2. Free Space Path Loss (FSPL)

$FSPL = (λ 4 π d)^{2} = (c 4 π fd)^{2}$

In dB:

$FSPL_{dB} = 20 log_{10} (d) + 20 log_{10} (f) + 32.44$

Where:

d = distance (km)
f = frequency (MHz)

3.3. Large-Scale Propagation Models

Okumura-Hata Model (Urban):

$L_{p} = 69.55 + 26.16 log_{10} (f) - 13.82 log_{10} (h_{b}) - a (h_{m}) + (44.9 - 6.55 log_{10} (h_{b})) log_{10} (d)$

Where:

$a (h_{m}) = (1.1 log_{10} (f) - 0.7) h_{m} - (1.56 log_{10} (f) - 0.8)$ (for medium-small city)
$a (h_{m}) = 8.29 [log_{10} (1.54 h_{m})]^{2} - 1.1$ (for large city, f ≤ 200 MHz)
$a (h_{m}) = 3.2 [log_{10} (11.75 h_{m})]^{2} - 4.97$ (for large city, f ≥ 400 MHz)

COST 231 Hata Model (Extended to 2 GHz):

$L_{p} = 46.3 + 33.9 log_{10} (f) - 13.82 log_{10} (h_{b}) - a (h_{m}) + (44.9 - 6.55 log_{10} (h_{b})) log_{10} (d) + C_{m}$

Where $C_{m} = 0$ dB (medium city), 3 dB (metropolitan)

Indoor Propagation (ITU Model):

$L_{p} = 20 log_{10} (f) + 37.5 + 20 log_{10} (d) + Wall Loss$

3.4. Small-Scale Fading

Multipath propagation causes:

Time dispersion (delay spread)
Frequency selective fading
Doppler spread
Time selective fading

Delay Spread (τ_rms):

RMS delay spread
Coherence bandwidth: $B_{c} \approx 1/ (2 π τ_{r m s})$

Doppler Shift:

$f_{d} = λ v cos θ$

Coherence time:

$T_{c} \approx f ^{d} 1$

3.5. Fading Types

Type	Channel	Frequency Response	Time Variation
Flat Fading	$B_{s} < B_{c}$	Non-selective	$T_{s} < T_{c}$
Frequency Selective	$B_{s} > B_{c}$	Selective	$T_{s} < T_{c}$
Fast Fading	$B_{s} < B_{c}$	Non-selective	$T_{s} > T_{c}$
Slow Fading	$B_{s} < B_{c}$	Non-selective	$T_{s} < T_{c}$

Where:

B_s = signal bandwidth
B_c = coherence bandwidth
T_s = symbol period
T_c = coherence time

3.6. Fading Distributions

Rayleigh Fading (No LOS):

$p (r) = σ ^{2} r e^{- r 2 / (2 σ 2)}, r \geq 0$

Rician Fading (LOS present):

$p (r) = σ ^{2} r e^{- (r 2 + A 2) / (2 σ 2)} I_{0} (σ ^{2} A r)$

K-factor (Rician):

$K = 2 σ ^{2} A ^{2} (dB: 10 log_{10} K)$

4. Modulation Techniques for Wireless

4.1. Digital Modulation Requirements for Wireless

Requirement	Description
Spectral efficiency	High bits/sec/Hz
Power efficiency	Low Eb/N0 required
Robustness	Resistant to fading, interference
Constant envelope	Allows nonlinear amplifiers

4.2. Phase Shift Keying (PSK)

BPSK (Binary PSK):

$s (t) = A cos (2 π f_{c} t + πm (t))$

Where m(t) = 0 or 1

QPSK (Quadrature PSK):

2 bits per symbol (4 phases: 45°, 135°, 225°, 315°)
Bandwidth efficiency: 2 bps/Hz

8-PSK:

3 bits per symbol (8 phases)
Bandwidth efficiency: 3 bps/Hz

π/4-QPSK:

Maximum phase change of 135° (vs. 180° for QPSK)
Reduced envelope variation

4.3. Quadrature Amplitude Modulation (QAM)

Modulation	Bits/Symbol	bps/Hz	Eb/N0 for BER=10⁻⁵
BPSK	1	1	9.6 dB
QPSK	2	2	9.6 dB
16-QAM	4	4	15.5 dB
64-QAM	6	6	21.0 dB
256-QAM	8	8	26.5 dB

4.4. Minimum Shift Keying (MSK)

Continuous phase (CPM)
Constant envelope
Good spectral efficiency
Used in GSM

Frequency deviation:

$Δ f = 4 T ^{b} 1$

Modulation index:

$h = 2Δ f \cdot T_{b} = 0.5$

4.5. Orthogonal Frequency Division Multiplexing (OFDM)

Principle: Multiple orthogonal subcarriers transmitted in parallel.

Subcarrier spacing:

$Δ f = T ^{s} 1$

Cyclic prefix (CP):

Guard interval to prevent ISI
CP length > channel delay spread

OFDM advantages:

Robust to multipath (frequency selective fading)
High spectral efficiency
Simple equalization

OFDM disadvantages:

High PAPR (Peak-to-Average Power Ratio)
Sensitive to frequency offset

5. Multiple Access Techniques

5.1. Frequency Division Multiple Access (FDMA)

Each user gets a dedicated frequency channel
Guard bands between channels
Used in 1G (AMPS)

5.2. Time Division Multiple Access (TDMA)

Each user gets a dedicated time slot
Frame structure
Used in 2G (GSM)

GSM frame structure:

1 TDMA frame = 8 time slots
1 time slot = 0.577 ms
1 frame = 4.615 ms

5.3. Code Division Multiple Access (CDMA)

All users share same frequency and time
Each user has unique spreading code
Based on spread spectrum technology

CDMA processing gain:

$G_{p} = R ^{b} W$

Where:

W = chip rate (bandwidth)
R_b = bit rate

CDMA capacity (single cell):

$M = 1 + SNR ^{req} G ^{p}$

5.4. Orthogonal Frequency Division Multiple Access (OFDMA)

Subcarriers allocated to different users
Used in 4G LTE, 5G NR
Flexible resource allocation

5.5. Space Division Multiple Access (SDMA)

Uses spatial separation (beamforming, MIMO)
Multiple users in same time/frequency/code

5.6. Comparison of Multiple Access Schemes

Feature	FDMA	TDMA	CDMA	OFDMA
Bandwidth per user	Dedicated	Shared	Shared	Shared
Synchronization	Not critical	Critical	Not critical	Moderate
Near-far problem	No	No	Yes	No
Interference	Adjacent channel	ISI	Multiple access	ICI
Used in	1G (AMPS)	2G (GSM)	2G (IS-95), 3G	4G, 5G

6. Diversity Techniques

6.1. Types of Diversity

Type	Description
Space Diversity	Multiple antennas (receive or transmit)
Time Diversity	Interleaving, ARQ
Frequency Diversity	Multiple carriers (OFDM, spread spectrum)
Polarization Diversity	Orthogonal polarizations

6.2. Receive Diversity

Selection Combining (SC):

Selects branch with highest SNR
Gain: $γ_{M} = γ \sum_{k = 1 M} k 1$

Maximal Ratio Combining (MRC):

Weights each branch by its SNR
Optimal combining
Gain: $γ_{M} = M γ$

Equal Gain Combining (EGC):

All branches weighted equally
Gain: $γ_{M} \approx M γ$ (for large M)

6.3. Transmit Diversity

Alamouti Scheme (2×1 MIMO):

Two transmit antennas, one receive
Space-time block coding
Full diversity (diversity order = 2)

Transmit matrix:

$X = [x^{1} x^{2} - x^{2 *} x^{1 *}]$

6.4. MIMO (Multiple Input Multiple Output)

MIMO gains:

Diversity gain (reliability)
Spatial multiplexing gain (capacity)
Array gain (SNR improvement)

MIMO capacity (with channel knowledge):

$C = B log_{2} det (I + N ^{t} SNR H H^{H})$

Capacity scaling:

$C \approx B min (N_{t}, N_{r}) log_{2} (SNR)$ (multiplexing)
$C \approx B log_{2} (1 + N_{t} N_{r} SNR)$ (diversity)

7. Wireless Standards

7.1. GSM (Global System for Mobile Communications)

Parameters:

Parameter	Value
Frequency bands	900 MHz, 1800 MHz, 1900 MHz
Duplex spacing	45 MHz (900), 95 MHz (1800)
Channel spacing	200 kHz
Multiple access	TDMA + FDMA
Modulation	GMSK
Voice coding	RPE-LTP (13 kbps)
Frame duration	4.615 ms
Time slots per frame	8

GSM Frame Structure:

Hyperframe: 2048 superframes
Superframe: 51 multiframes (traffic) or 26 multiframes (control)
Multiframe: 26 or 51 TDMA frames
TDMA frame: 8 time slots
Time slot: 0.577 ms (148 bits)

7.2. GPRS (General Packet Radio Service)

Parameters:

Data rate: up to 171.2 kbps (theoretical)
Coding schemes: CS-1 to CS-4 (9.05 to 21.4 kbps per slot)
Multislot classes: up to 8 slots

7.3. EDGE (Enhanced Data rates for GSM Evolution)

Parameters:

Modulation: 8-PSK (vs. GMSK for GSM)
Data rate: up to 473.6 kbps (theoretical)
Coding schemes: MCS-1 to MCS-9

7.4. UMTS (3G WCDMA)

Parameters:

Parameter	Value
Frequency bands	850, 900, 1700, 1900, 2100 MHz
Channel spacing	5 MHz
Multiple access	WCDMA + CDMA
Modulation	QPSK (downlink), BPSK (uplink)
Chip rate	3.84 Mcps
Voice coding	AMR (4.75-12.2 kbps)

HSPA (High Speed Packet Access):

HSDPA: up to 14.4 Mbps (downlink)
HSUPA: up to 5.76 Mbps (uplink)
Modulation: 16-QAM (downlink), BPSK/QPSK (uplink)

7.5. LTE (Long Term Evolution) – 4G

Parameters:

Parameter	Value
Frequency bands	700 MHz to 2.6 GHz (70+ bands)
Channel bandwidths	1.4, 3, 5, 10, 15, 20 MHz
Multiple access	OFDMA (downlink), SC-FDMA (uplink)
Modulation	QPSK, 16-QAM, 64-QAM, 256-QAM
MIMO	Up to 4×4 (downlink), 2×2 (uplink)
Peak data rate	100 Mbps (downlink), 50 Mbps (uplink) (Cat 3)
LTE-Advanced	1 Gbps (downlink), 500 Mbps (uplink)

LTE Frame Structure (FDD):

1 radio frame = 10 ms (10 subframes × 1 ms)
1 subframe = 1 ms (2 slots × 0.5 ms)
1 slot = 7 OFDM symbols (normal CP)

Resource block:

1 RB = 12 subcarriers × 7 symbols = 84 resource elements
Subcarrier spacing: 15 kHz
RB bandwidth: 180 kHz

7.6. 5G NR (New Radio)

Parameters:

Parameter	Value
Frequency Range 1 (FR1)	410 MHz – 7.125 GHz (Sub-6 GHz)
Frequency Range 2 (FR2)	24.25 – 52.6 GHz (mmWave)
Channel bandwidths	5-400 MHz (FR1), 50-800 MHz (FR2)
Subcarrier spacing	15, 30, 60, 120, 240 kHz
Modulation	QPSK, 16-QAM, 64-QAM, 256-QAM
MIMO	Up to 32×32 (downlink), 8×8 (uplink)
Peak data rate	Up to 20 Gbps (downlink)

5G Use Cases:

Use Case	Requirements
eMBB (Enhanced Mobile Broadband)	High data rate, high capacity
URLLC (Ultra-Reliable Low Latency)	1 ms latency, 99.999% reliability
mMTC (Massive Machine Type Comm)	1 million devices/km²

7.7. Wireless Local Area Networks (WLAN)

IEEE 802.11 Standards (Wi-Fi):

Standard	Frequency	Max Data Rate	Modulation	MIMO
802.11b	2.4 GHz	11 Mbps	DSSS, CCK	No
802.11a	5 GHz	54 Mbps	OFDM	No
802.11g	2.4 GHz	54 Mbps	OFDM	No
802.11n	2.4/5 GHz	600 Mbps	OFDM	Yes (4×4)
802.11ac	5 GHz	6.9 Gbps	OFDM	Yes (8×8)
802.11ax (Wi-Fi 6)	2.4/5 GHz	9.6 Gbps	OFDMA	Yes (8×8)

7.8. Bluetooth (IEEE 802.15.1)

Parameters:

Parameter	Classic	BLE
Frequency	2.4 GHz	2.4 GHz
Channels	79 (1 MHz)	40 (2 MHz)
Data rate	1-3 Mbps	1-2 Mbps
Range	10-100 m	10-30 m
Power consumption	Medium	Very low
Modulation	GFSK	GFSK

7.9. ZigBee (IEEE 802.15.4)

Parameters:

Parameter	Value
Frequency	868 MHz (EU), 915 MHz (US), 2.4 GHz (global)
Data rate	20-250 kbps
Range	10-100 m
Power consumption	Very low
Modulation	BPSK, O-QPSK

8. Wireless Security

8.1. Security Threats

Threat	Description
Eavesdropping	Intercepting communications
Jamming	Deliberate interference
Man-in-the-Middle	Intercepting and modifying
Replay attack	Retransmitting captured data
Rogue base station	Impersonating legitimate base station

8.2. Security Measures

Measure	Description
Encryption	A5/1, A5/3 (GSM), KASUMI (3G), AES (4G/5G)
Authentication	SIM/USIM card, mutual authentication
Integrity protection	Message authentication codes
Subscriber identity protection	TMSI (Temporary Mobile Subscriber Identity)

8.3. GSM Security

Subscriber authentication using Ki (128-bit)
Encryption key (Kc) derived from Ki and random challenge
A5/1 stream cipher (broken, not secure)

8.4. 3G/4G/5G Security

Mutual authentication (network authenticates to UE)
Longer keys (128-bit)
Stronger algorithms (KASUMI, AES, SNOW 3G, ZUC)
Integrity protection for signaling

9. Key Equations Reference Sheet

Equation	Description
$Q = D / R = 3 N$	Co-channel reuse ratio
$P_{b} = \sum ^{k = 0 C} A ^{k} / k ! A ^{C} / C !$	Erlang B formula
$FSPL_{dB} = 20 log_{10} (d) + 20 log_{10} (f) + 32.44$	Free space path loss
$f_{d} = λ v cos θ$	Doppler shift
$p (r) = σ ^{2} r e^{- r 2 / (2 σ 2)}$	Rayleigh distribution
$G_{p} = W / R_{b}$	CDMA processing gain
$C = B log_{2} det (I + SNR / N_{t} HH^{H})$	MIMO capacity

10. Standard Textbooks

Author	Title	Focus
Rappaport, T.S.	Wireless Communications: Principles and Practice	Comprehensive
Goldsmith, A.	Wireless Communications	Theoretical
Molisch, A.F.	Wireless Communications	In-depth
Tse & Viswanath	Fundamentals of Wireless Communication	Information theory focus

11. Final Study Checklist

Topic	Key Skills
Cellular Concepts	Calculate reuse factor, capacity, Erlang B
Propagation	Apply path loss models; distinguish fading types
Modulation	Compare PSK, QAM, OFDM; calculate spectral efficiency
Multiple Access	Compare FDMA, TDMA, CDMA, OFDMA
Diversity	Calculate combining gains; explain MIMO benefits
GSM	Describe frame structure, channels, handover
LTE/5G	Explain OFDMA, frame structure, resource blocks
Wireless Security	Identify threats; explain authentication and encryption

TE-366: Digital Signal Processing – Comprehensive Study Notes

These notes provide a complete framework for Digital Signal Processing (DSP) , covering the mathematical representation, analysis, and manipulation of discrete-time signals. The focus is on understanding the fundamental principles of converting continuous signals to digital form, analyzing signals in both time and frequency domains, and designing digital filters for practical applications .

Part 1: Fundamentals of Digital Signal Processing

1.1 What is Digital Signal Processing?

Digital Signal Processing (DSP) is the mathematical manipulation of discrete-time signals using digital computers or specialized hardware. It has revolutionized many fields including audio processing, telecommunications, radar, biomedical engineering, and image processing .

Advantages of Digital over Analog Processing:

Advantage	Description
Reproducibility	No component tolerance variations; identical performance every time
Flexibility	Easily reprogrammable; same hardware can perform different functions
Precision	Limited only by word length (number of bits)
No drift	No aging or temperature effects on performance
Complex algorithms	Can implement functions impossible in analog (adaptive filters, FFT)
Storage capability	Digital signals can be stored and retrieved exactly

1.2 Signal Classification

Signal Type	Continuous Domain	Discrete Domain
Analog Signal	Continuous in time, continuous in amplitude	–
Discrete-time Signal	Discrete in time, continuous in amplitude	Sequence $x [n]$
Digital Signal	Discrete in time, quantized in amplitude	Finite-precision sequence

Analog Signal: Continuous in both time and amplitude (e.g., natural speech, music, temperature).

Discrete-time Signal: Defined only at discrete time instants (sampling instants). Represented as a sequence: $x [n]$ , where $n$ is an integer index.

Digital Signal: Discrete in both time and amplitude—both sampling (time discretization) and quantization (amplitude discretization) have been applied.

1.3 The DSP System Block Diagram

┌─────────────┐    ┌─────────────┐    ┌─────────────┐    ┌─────────────┐    ┌─────────────┐
│   Analog    │    │  Sample &   │    │    A/D      │    │  Digital    │    │    D/A      │
│   Input     │───▶│   Hold      │───▶│ Converter   │───▶│  Processor  │───▶│ Converter   │
│   Signal    │    │             │    │             │    │    (DSP)    │    │             │
└─────────────┘    └─────────────┘    └─────────────┘    └──────┬──────┘    └──────┬──────┘
                                                                │                  │
                                                          ┌─────▼─────┐      ┌─────▼─────┐
                                                          │  Digital  │      │  Smoothing│
                                                          │  Output   │◀─────│  Filter   │
                                                          │  (Binary) │      │           │
                                                          └───────────┘      └───────────┘

Key Stages :

Anti-aliasing filter: Analog low-pass filter that removes frequencies above half the sampling rate
Sample and Hold: Captures instantaneous analog value at sampling instants
Analog-to-Digital Converter (ADC) : Converts analog samples to binary numbers
Digital Signal Processor: Performs mathematical operations (filtering, correlation, etc.)
Digital-to-Analog Converter (DAC) : Converts processed digital data back to analog
Smoothing filter: Removes high-frequency artifacts from the staircase DAC output

Part 2: Discrete-Time Signals and Systems

2.1 Discrete-Time Signal Representation

A discrete-time signal is represented as a sequence: $x [n]$ , where $n$ is an integer index representing discrete time (sample number).

Common Discrete-Time Signals:

Signal	Notation	Example
Unit impulse (Kronecker delta)	$δ [n] = {1, 0, n = 0 n \neq = 0$	$[\dots, 0, 1, 0, \dots]$
Unit step	$u [n] = {1, 0, n \geq 0 n < 0$	$[\dots, 0, 1, 1, 1, \dots]$
Exponential	$x [n] = a^{n}$	Geometric progression
Sinusoidal	$x [n] = A cos (ωn + ϕ)$	Sampled sinusoid
Rectangular window	$R_{N} [n] = {1, 0, 0 \leq n < N otherwise$	Finite-length signal

2.2 Basic Operations on Signals

Operation	Mathematical Definition	Example
Shift (Delay)	$y [n] = x [n - k]$	Delay by k samples
Fold (Time reversal)	$y [n] = x [- n]$	Reflection about n=0
Addition	$y [n] = x_{1} [n] + x_{2} [n]$	Superposition
Multiplication	$y [n] = x_{1} [n] \cdot x_{2} [n]$	Modulation
Scaling (amplitude)	$y [n] = a \cdot x [n]$	Amplify or attenuate
Decimation (downsampling)	$y [n] = x [M n]$	Reduce sampling rate by factor M
Interpolation (upsampling)	$y [n] = {x [n / L], 0, n multiple of L otherwise$	Increase sampling rate by factor L

2.3 Linear Time-Invariant (LTI) Systems

Definition: A system $T {\cdot}$ is Linear and Time-Invariant (LTI) if it satisfies:

Property	Mathematical Condition
Linearity (Superposition)	$T {a x_{1} [n] + b x_{2} [n]} = a T {x_{1} [n]} + b T {x_{2} [n]}$
Time Invariance	If $y [n] = T {x [n]}$ , then $y [n - k] = T {x [n - k]}$

Significance: LTI systems are completely characterized by their impulse response $h [n]$ (system output when input is $δ [n]$ ).

2.4 Convolution (Time-Domain Input-Output Relationship)

For an LTI system with impulse response $h [n]$ , the output for any input $x [n]$ is given by convolution :

$y [n] = x [n] * h [n] = k = -\infty \sum \infty x [k] h [n - k] = k = -\infty \sum \infty h [k] x [n - k]$

Properties of Convolution :

Property	Expression
Commutative	$x [n] * h [n] = h [n] * x [n]$
Associative	$(x [n] * h_{1} [n]) * h_{2} [n] = x [n] * (h_{1} [n] * h_{2} [n])$
Distributive	$x [n] * (h_{1} [n] + h_{2} [n]) = x [n] * h_{1} [n] + x [n] * h_{2} [n]$
Identity	$x [n] * δ [n] = x [n]$
Shift	$x [n] * δ [n - k] = x [n - k]$

2.5 System Properties from Impulse Response

Property	Condition on $h [n]$
Causal	$h [n] = 0$ for $n < 0$ (output depends only on past and present inputs)
Stable (BIBO)	( \sum_{n=-\infty}^{\infty}	h[n]	< \infty )
Finite Impulse Response (FIR)	$h [n] = 0$ outside a finite interval
Infinite Impulse Response (IIR)	$h [n]$ has infinite duration

2.6 Difference Equations

LTI systems can be described by constant-coefficient linear difference equations :

$y [n] = - k = 1 \sum N a_{k} y [n - k] + k = 0 \sum M b_{k} x [n - k]$

Special Cases :

Type	Difference Equation	Characteristic
FIR (Moving Average)	$y [n] = \sum_{k = 0 M} b_{k} x [n - k]$	No feedback; stable; linear phase possible
IIR (Autoregressive)	$y [n] = - \sum_{k = 1 N} a_{k} y [n - k] + b_{0} x [n]$	Feedback; potentially unstable; requires care in design

Part 3: Sampling and Reconstruction

3.1 The Sampling Theorem (Nyquist-Shannon)

The Sampling Theorem: A continuous-time signal $x (t)$ with band-limited spectrum (no frequency components above $f_{ma x}$ Hz) can be uniquely recovered from its samples if the sampling frequency $f_{s}$ is greater than $2 f_{ma x}$ :

$f_{s} > 2 f_{ma x}$

Nyquist Rate: The minimum sampling rate to avoid aliasing is $f_{N y q u i s t} = 2 f_{ma x}$ .

3.2 Aliasing

Aliasing occurs when a signal is sampled below the Nyquist rate. High-frequency components “fold back” into the low-frequency range, becoming indistinguishable from legitimate low-frequency signals.

Mathematical Description :
If $X (f)$ is the spectrum of the continuous signal, the spectrum of the sampled signal $X_{s} (f)$ is:

$X_{s} (f) = T ^{s} 1 k = -\infty \sum \infty X (f - k f_{s})$

Where $T_{s} = 1/ f_{s}$ is the sampling period.

Preventing Aliasing :

Anti-aliasing filter: Low-pass filter applied before sampling to remove frequencies above $f_{s} /2$
Choose $f_{s}$ sufficiently high (typically 2.5-5 times $f_{ma x}$ in practice)

3.3 Quantization

Quantization is the process of mapping a continuous amplitude to a finite set of discrete levels .

Quantization Parameters :

Parameter	Formula	Example
Number of levels	$L = 2^{B}$ (B = number of bits)	8 bits → 256 levels
Quantization step size	$Δ = L Range$	Range 10V, 256 levels → $Δ \approx 0.039$ V
Quantization error	$e_{q} [n] = x_{q} [n] - x [n]$	Random, uniformly distributed

Quantization Noise :

Mean squared error: $σ_{e 2} = 12 Δ ^{2}$
Signal-to-Quantization Noise Ratio (SQNR) : $SQNR = 6.02 B + 1.76$ dB (for full-scale sine wave)

This formula shows each additional bit improves SQNR by approximately 6 dB .

3.4 Reconstruction

Ideal Reconstruction uses a low-pass filter (sinc interpolation) to reconstruct the continuous signal from its samples:

$x (t) = n = -\infty \sum \infty x [n] \cdot sinc (T ^{s} t - n T ^{s})$

Practical Reconstruction uses a zero-order hold (DAC followed by smoothing filter), which approximates the ideal reconstruction with staircase output.

Part 4: The Z-Transform

4.1 Definition

The Z-transform is the discrete-time equivalent of the Laplace transform. It is the fundamental tool for analyzing discrete-time systems .

Bilateral Z-transform:

$X (z) = Z {x [n]} = n = -\infty \sum \infty x [n] z^{- n}$

Unilateral Z-transform (for causal signals):

$X (z) = n = 0 \sum \infty x [n] z^{- n}$

Where $z$ is a complex variable ( $z = r e^{jω}$ ).

4.2 Region of Convergence (ROC)

The Region of Convergence (ROC) is the set of $z$ for which the Z-transform converges (the infinite sum is finite). The ROC is essential for uniqueness of the inverse Z-transform.

ROC Properties :

ROC is a ring or disk centered at the origin
ROC cannot contain any poles
For causal sequences, ROC is outside the outermost pole
For anti-causal sequences, ROC is inside the innermost pole
For finite-length sequences, ROC is the entire z-plane except possibly $z = 0$ and $z = \infty$

4.3 Common Z-Transform Pairs

Signal $x [n]$	Z-transform $X (z)$	ROC
$δ [n]$	1	All $z$
$δ [n - k]$	$z^{- k}$	All $z$ , $z \neq = 0$
$u [n]$	$1 - z ^{-1} 1$	(	z	> 1 )
$- u [- n - 1]$	$1 - z ^{-1} 1$	(	z	< 1 )
$a^{n} u [n]$	$1 - a z ^{-1} 1$	(	z	>	a	)
$- a^{n} u [- n - 1]$	$1 - a z ^{-1} 1$	(	z	<	a	)
$n a^{n} u [n]$	$( 1 - a z ^{-1} ) ^{2} a z ^{-1}$	(	z	>	a	)
$cos (ω_{0} n) u [n]$	$1 - 2 c o s ( ω ^{0} ) z ^{-1} + z ^{-2} 1 - c o s ( ω ^{0} ) z ^{-1}$	(	z	> 1 )
$sin (ω_{0} n) u [n]$	$1 - 2 c o s ( ω ^{0} ) z ^{-1} + z ^{-2} s i n ( ω ^{0} ) z ^{-1}$	(	z	> 1 )

4.4 Z-Transform Properties

Property	Time Domain	Z-Domain	ROC
Linearity	$a x_{1} [n] + b x_{2} [n]$	$a X_{1} (z) + b X_{2} (z)$	At least intersection of ROCs
Time shift (causal)	$x [n - k]$ (k>0)	$z^{- k} X (z)$	(	z	> R ) (except possible $z = 0$ )
Time shift (non-causal)	$x [n + k]$ (k>0)	$z^{k} X (z)$	(	z	> R ) (except possible $z = \infty$ )
Convolution	$x_{1} [n] * x_{2} [n]$	$X_{1} (z) X_{2} (z)$	At least intersection of ROCs
Multiplication by n	$n x [n]$	$- z d z d X ( z )$	Same as $X (z)$
Time reversal	$x [- n]$	$X (z^{-1})$	Inverted ROC
Initial value theorem	$x [0] = lim_{z \to \infty} X (z)$	For causal sequences	–
Final value theorem	$lim_{n \to \infty} x [n] = lim_{z \to 1} (1 - z^{-1}) X (z)$	For causal sequences with ROC including unit circle	–

4.5 Transfer Function

For an LTI system with impulse response $h [n]$ , the transfer function $H (z)$ is the Z-transform of $h [n]$ :

$H (z) = X ( z ) Y ( z )$

For systems described by a difference equation:

$k = 0 \sum N a_{k} y [n - k] = k = 0 \sum M b_{k} x [n - k]$

Taking Z-transform (assuming initial conditions zero):

$H (z) = \sum ^{k = 0 N} a ^{k} z ^{- k} \sum ^{k = 0 M} b ^{k} z ^{- k} = a ^{0} + a ^{1} z ^{-1} + \dots + a ^{N} z ^{- N} b ^{0} + b ^{1} z ^{-1} + \dots + b ^{M} z ^{- M}$

4.6 Poles and Zeros

The transfer function can be factored as:

$H (z) = K ( z - p ^{1} ) ( z - p ^{2} ) \dots ( z - p ^{N} ) ( z - z ^{1} ) ( z - z ^{2} ) \dots ( z - z ^{M} )$

Where:

Zeros: Values of $z$ where $H (z) = 0$ (roots of numerator)
Poles: Values of $z$ where $H (z) = \infty$ (roots of denominator)

Stability Condition: An LTI system is BIBO stable if and only if all poles lie inside the unit circle ( $∣ p_{i} ∣ < 1$ for all $i$ ).

Part 5: Frequency Domain Analysis

5.1 Discrete-Time Fourier Transform (DTFT)

The Discrete-Time Fourier Transform (DTFT) is the frequency-domain representation of a discrete-time signal.

DTFT Definition:

$X (e^{jω}) = n = -\infty \sum \infty x [n] e^{- jωn}$

Where $ω$ is the normalized radian frequency (in radians per sample).

Inverse DTFT:

$x [n] = 2 π 1 \int_{- π π} X (e^{jω}) e^{jωn} d ω$

Key Properties of DTFT :

Property	Description
Periodicity	$X (e^{j (ω + 2 π)}) = X (e^{o m e g a})$
Symmetry (real x[n])	$X (e^{- jω}) = X^{*} (e^{jω})$
Convolution	$x [n] * h [n] D TFT X (e^{jω}) H (e^{jω})$
Multiplication	$x [n] y [n] D TFT 2 π 1 X (e^{jω}) * Y (e^{jω})$ (circular convolution)

5.2 Frequency Response of LTI Systems

For an LTI system with impulse response $h [n]$ , the frequency response is the DTFT of $h [n]$ :

$H (e^{jω}) = n = -\infty \sum \infty h [n] e^{- jωn}$

When the input is a complex exponential $x [n] = e^{jωn}$ , the output is:

$y [n] = H (e^{jω}) e^{jωn}$

Thus, $H (e^{jω})$ is the gain and phase shift applied by the system at frequency $ω$ .

Magnitude Response: $∣ H (e^{jω}) ∣$
Phase Response: $∠ H (e^{jω})$

5.3 Relationship Between DTFT and Z-Transform

The DTFT is the Z-transform evaluated on the unit circle:

$X (e^{jω}) = X (z)_{z = e jω}$

This relationship holds when the ROC includes the unit circle.

5.4 The Discrete Fourier Transform (DFT)

The Discrete Fourier Transform (DFT) is a sampled version of the DTFT, computed for a finite-length sequence of length $N$ .

DFT Definition:

$X [k] = n = 0 \sum N - 1 x [n] e^{- j 2 πkn / N}, k = 0, 1, \dots, N - 1$

Inverse DFT (IDFT) :

$x [n] = N 1 k = 0 \sum N - 1 X [k] e^{j 2 πkn / N}, n = 0, 1, \dots, N - 1$

DFT Properties:

Property	Time Domain	Frequency Domain
Linearity	$a x_{1} [n] + b x_{2} [n]$	$a X_{1} [k] + b X_{2} [k]$
Circular shift	$x [(n - m) mod N]$	$X [k] e^{- j 2 πkm / N}$
Circular convolution	$x_{1} [n] ⊛ x_{2} [n]$	$X_{1} [k] X_{2} [k]$
Modulation	$x [n] e^{j 2 πmn / N}$	$X [(k - m) mod N]$

Circular convolution is defined as:

$y [n] = m = 0 \sum N - 1 x_{1} [m] x_{2} [(n - m) mod N]$

5.5 Fast Fourier Transform (FFT)

The Fast Fourier Transform (FFT) is an efficient algorithm to compute the DFT with complexity $O (N log N)$ instead of $O (N^{2})$ .

Cooley-Tukey Radix-2 FFT (N is power of 2):

Decimation-in-time (DIT) : Split into even and odd index samples
Decimation-in-frequency (DIF) : Split into first and second halves

Complexity Comparison:

N	Direct DFT (O(N²))	FFT (O(N log₂ N))	Ratio
64	4,096	384	10.7×
256	65,536	2,048	32×
1,024	1,048,576	10,240	102×
4,096	16,777,216	49,152	341×

5.6 Windowing

When taking the DFT of a finite segment of a longer signal, the abrupt truncation causes spectral leakage (energy spreads from the true frequency to neighboring bins). Windowing reduces this effect.

Common Window Functions :

Window	Time Domain (0 ≤ n < N)	Main Lobe Width	Peak Sidelobe (dB)	Scallop Loss (dB)
Rectangular	1	4π/N	-13	3.92
Hanning	$0.5 - 0.5 cos (2 πn / (N - 1))$	8π/N	-31	1.78
Hamming	$0.54 - 0.46 cos (2 πn / (N - 1))$	8π/N	-41	1.78
Blackman	$0.42 - 0.5 cos (2 πn / (N - 1)) + 0.08 cos (4 πn / (N - 1))$	12π/N	-57	1.25
Kaiser	$I_{0} (β 1 - (2 n / (N - 1) - 1)^{2}) / I_{0} (β)$	Adjustable	Adjustable	Adjustable

The Kaiser window uses the parameter $β$ to trade off main lobe width against sidelobe levels .

Part 6: Digital Filters

6.1 Filter Classification

Classification	Types
By length	FIR (Finite Impulse Response), IIR (Infinite Impulse Response)
By frequency response	Low-pass, High-pass, Band-pass, Band-stop (Notch), All-pass
By implementation	Direct form, Cascade form, Parallel form, Lattice
By phase response	Linear phase, Minimum phase, Maximum phase

6.2 FIR Filters

Characteristics :

Impulse response has finite length
Always stable (poles at origin only)
Can have exactly linear phase (by making coefficients symmetric or anti-symmetric)
Generally higher order than IIR for same specifications

Difference Equation (order M):

$y [n] = k = 0 \sum M b_{k} x [n - k]$

Transfer Function:

$H (z) = b_{0} + b_{1} z^{-1} + \dots + b_{M} z^{- M}$

Linear Phase Conditions (for symmetry/anti-symmetry about center):

Type	Symmetry	Length	Frequency Response	Typical Use
I	Symmetric ( $h [n] = h [M - n]$ )	Odd	All filters	General purpose
II	Symmetric	Even	Not suitable for high-pass	Efficient half-band filters
III	Anti-symmetric ( $h [n] = - h [M - n]$ )	Odd	Zero at ω=0	Hilbert transformers, differentiators
IV	Anti-symmetric	Even	Zero at ω=0 and ω=π	Hilbert transformers, differentiators

6.3 IIR Filters

Characteristics :

Impulse response has infinite duration (due to feedback)
Can be unstable if poles outside unit circle
More efficient (lower order) than FIR for same magnitude response
Nonlinear phase (unless using special structures)

Difference Equation (order N):

$y [n] = - k = 1 \sum N a_{k} y [n - k] + k = 0 \sum M b_{k} x [n - k]$

Transfer Function:

$H (z) = 1 + a ^{1} z ^{-1} + \dots + a ^{N} z ^{- N} b ^{0} + b ^{1} z ^{-1} + \dots + b ^{M} z ^{- M}$

Stability: All poles must lie inside the unit circle ( $∣ p_{i} ∣ < 1$ ).

6.4 IIR Filter Design Methods

Method	Description	Characteristics
Butterworth	Maximally flat magnitude response	Smooth passband, gradual roll-off
Chebyshev Type I	Equal ripple in passband	Sharper roll-off, ripple in passband
Chebyshev Type II	Equal ripple in stopband	Sharper roll-off, ripple in stopband
Elliptic (Cauer)	Equal ripple in both bands	Sharpest roll-off, ripple in both bands
Bessel	Maximally flat group delay	Linear phase, poor magnitude response

Analog Prototype to Digital Conversion Methods :

Method	Description	Mapping
Impulse Invariance	Preserves impulse response	$h [n] = h_{c} (n T)$
Bilinear Transform	Maps analog to digital frequency	$s = T 2 1 + z ^{-1} 1 - z ^{-1}$

The bilinear transform warps the frequency axis (pre-warping needed), but avoids aliasing issues of impulse invariance .

6.5 Filter Implementation Structures

Direct Form I :

Separate delay lines for input and output
Most straightforward
More memory than other forms

Direct Form II (Canonic) :

Shares delay line for input and output
Fewer memory elements
Potential scaling issues

Cascade Form :

Second-order sections (biquads) in series
More robust to coefficient quantization
Easier to adjust individual sections

Parallel Form :

Partial fraction expansion
Second-order sections in parallel
Each section independent

6.6 Biquad (Second-Order Section)

The biquad is the fundamental building block for digital filters (both FIR and IIR) .

Transfer Function:

$H (z) = 1 + a ^{1} z ^{-1} + a ^{2} z ^{-2} b ^{0} + b ^{1} z ^{-1} + b ^{2} z ^{-2}$

Direct Form II Transposed (most common for fixed-point implementation) :

Less sensitive to coefficient quantization
Better scaling properties
Used in most DSP libraries and code generation tools

Part 7: Key Formulas Summary

Concept	Formula
Nyquist rate	$f_{s} > 2 f_{ma x}$
Quantization step	$Δ = Range / 2^{B}$
SQNR (dB)	$SQNR = 6.02 B + 1.76$ dB
Z-transform	$X (z) = \sum x [n] z^{- n}$
DTFT	$X (e^{jω}) = \sum x [n] e^{- jωn}$
DFT	$X [k] = \sum_{n = 0 N - 1} x [n] e^{- j 2 πkn / N}$
Convolution	$y [n] = \sum_{k} x [k] h [n - k]$
Circular convolution	$y [n] = \sum_{m = 0 N - 1} x_{1} [m] x_{2} [(n - m) mod N]$
FIR transfer function	$H (z) = \sum_{k = 0 M} b_{k} z^{- k}$
IIR transfer function	$H (z) = (\sum b_{k} z^{- k}) / (1 + \sum a_{k} z^{- k})$
Stability condition	All poles (	p_i	< 1 )
Bilinear transform	$s = T 2 1 + z ^{-1} 1 - z ^{-1}$

Part 8: Study Tips for TE-366

Master the fundamental sequences – Know $δ [n]$ , $u [n]$ , their properties, and their relationships.
Understand the Z-transform properties – Especially linearity, time shifting, and convolution. These are used constantly.
Practice convolution – Work through graphical, tabular, and direct summation methods. Convolution is central to DSP.
Learn the DTFT and DFT relationship – The DFT is a sampled version of the DTFT. Understand aliasing in frequency domain.
Know the FFT – Understand why it’s efficient (O(N log N) vs. O(N²)). Know the basic radix-2 decimation-in-time structure.
Distinguish FIR from IIR – FIR: stable, linear phase possible, higher order. IIR: more efficient, potentially unstable, nonlinear phase.
Understand the bilinear transform – Know that it maps the analog jω axis to the digital unit circle, and why pre-warping is needed.
Practice filter design – Work through examples of Butterworth, Chebyshev, and elliptic designs. Understand the trade-offs.
Connect to other courses – TE-366 builds on signals and systems, and prepares you for advanced communications, image processing, and machine learning.
Use software tools – MATLAB, Python (NumPy/SciPy), or Octave can help visualize signals, compute FFTs, and design filters. The UTRGV course specifically mentions MATLAB for assignments .

Part 9: Recommended Textbooks and Resources

Resource	Focus
Discrete-Time Signal Processing – Oppenheim & Schafer	Comprehensive, rigorous standard text
Digital Signal Processing: Principles, Algorithms, and Applications – Proakis & Manolakis	Practical, algorithm-focused
Understanding Digital Signal Processing – Richard Lyons	Accessible, intuitive explanations
Digital Signal Processing – Mitra	Strong on filter design
Signals and Systems – Oppenheim & Willsky	Prerequisite material

These notes provide a comprehensive framework for TE-366: Digital Signal Processing. Success requires understanding the sampling theorem (Nyquist rate, aliasing), mastering transform analysis (Z-transform, DTFT, DFT/FFT), applying convolution (time-domain system response), and designing digital filters (FIR vs. IIR trade-offs, stability, implementation). DSP is fundamental to modern communications, audio, image processing, radar, biomedical engineering, and countless other fields—essential knowledge for electrical and computer engineers.

TE-368 Information and Network Security – Detailed Study Notes

These study notes are designed for undergraduate engineering students taking a course in Information and Network Security. The notes cover the fundamental principles of cryptography, network security protocols, system security, and emerging security challenges.

1. Introduction to Information Security

1.1 What is Information Security?

Aspect	Detail
Definition	Information security is the practice of protecting information from unauthorized access, use, disclosure, disruption, modification, or destruction.
Key Objectives (CIA Triad)	Confidentiality (preventing unauthorized disclosure), Integrity (preventing unauthorized modification), Availability (ensuring timely and reliable access)
Additional Objectives	Authentication (verifying identity), Authorization (access control), Non-repudiation (proof of origin), Accountability (audit trail)

1.2 Types of Security Threats

Threat Type	Description	Examples
Passive attacks	Eavesdropping, monitoring	Traffic analysis, packet sniffing
Active attacks	Modification, disruption	Masquerade, replay, DoS
Insider threats	Internal malicious actors	Disgruntled employees
Malware	Malicious software	Viruses, worms, Trojans, ransomware
Social engineering	Human manipulation	Phishing, pretexting, baiting

1.3 Security Services (X.800)

Service	Description
Authentication	Assurance that communicating entity is who it claims to be
Access control	Prevention of unauthorized use of resources
Data confidentiality	Protection of data from unauthorized disclosure
Data integrity	Assurance that data has not been altered
Non-repudiation	Protection against denial of sending or receiving
Availability	Assurance that resources are accessible

2. Cryptographic Fundamentals

2.1 Symmetric Key Cryptography

Aspect	Detail
Principle	Same key for encryption and decryption
Advantages	Fast, efficient for bulk data
Disadvantages	Key distribution problem
Algorithms	DES, 3DES, AES, RC4, Blowfish, Twofish

AES (Advanced Encryption Standard):

Block size: 128 bits
Key sizes: 128, 192, 256 bits
Rounds: 10 (128-bit key), 12 (192-bit), 14 (256-bit)
Operations: SubBytes, ShiftRows, MixColumns, AddRoundKey

DES (Data Encryption Standard):

Block size: 64 bits
Key size: 56 bits (effective)
Rounds: 16
Feistel network structure
Now considered insecure

3DES (Triple DES):

Three DES operations: encrypt-decrypt-encrypt (EDE)
Effective key: 112 or 168 bits
Still secure but slow

2.2 Asymmetric (Public Key) Cryptography

Aspect	Detail
Principle	Two keys: public (encryption), private (decryption)
Advantages	Solves key distribution; provides digital signatures
Disadvantages	Slower than symmetric (100-1000×)
Algorithms	RSA, ECC, Diffie-Hellman, DSA, ElGamal

RSA Algorithm:

1. Choose two large primes p and q
2. Compute n = p × q, φ(n) = (p-1)(q-1)
3. Choose e such that 1 < e < φ(n) and gcd(e, φ(n)) = 1
4. Compute d such that d × e ≡ 1 mod φ(n)
5. Public key: (e, n); Private key: (d, n)
6. Encryption: C = M^e mod n
7. Decryption: M = C^d mod n

Diffie-Hellman Key Exchange:

1. Agree on prime p and primitive root g
2. Alice: chooses private a, sends A = g^a mod p
3. Bob: chooses private b, sends B = g^b mod p
4. Shared secret: K = B^a mod p = A^b mod p = g^{ab} mod p

Note: Provides key agreement, not encryption

ECC (Elliptic Curve Cryptography):

Based on elliptic curve discrete logarithm problem
Shorter key lengths for same security (256-bit ECC ≈ 3072-bit RSA)
Faster, lower power consumption

2.3 Hash Functions

Aspect	Detail
Definition	One-way function producing fixed-size output (digest)
Properties	Preimage resistance, second preimage resistance, collision resistance
Algorithms	MD5 (broken), SHA-1 (weak), SHA-256, SHA-3

Common Hash Algorithms:

Algorithm	Output Size (bits)	Security Status
MD5	128	Broken (collisions found)
SHA-1	160	Weak (deprecated)
SHA-256	256	Secure
SHA-512	512	Secure
SHA-3	224, 256, 384, 512	Secure

2.4 Message Authentication Codes (MAC)

Aspect	Detail
Definition	Keyed hash function providing integrity and authentication
Examples	HMAC (Hash-based MAC), CMAC (Cipher-based MAC)
HMAC	HMAC(K,m) = H[(K ⊕ opad)	H[(K ⊕ ipad)	m]]

2.5 Digital Signatures

Aspect	Detail
Purpose	Authentication, integrity, non-repudiation
Process (RSA)	Sign: hash → encrypt with private key → signature Verify: hash → decrypt signature with public key → compare
Standards	RSA-PSS, DSA, ECDSA

2.6 Public Key Infrastructure (PKI)

Component	Function
Certificate Authority (CA)	Issues and verifies digital certificates
Registration Authority (RA)	Verifies identity before certificate issuance
Certificate Revocation List (CRL)	Lists revoked certificates
X.509 certificate	Standard format for digital certificates

X.509 Certificate Fields:

Version, Serial number, Signature algorithm
Issuer name, Validity period, Subject name
Subject public key info, Extensions, Signature

3. Network Security Protocols

3.1 TCP/IP Security

Layer	Protocol	Security Issues	Security Solutions
Application	HTTP, FTP, SMTP	Plaintext transmission	HTTPS, SFTP, S/MIME
Transport	TCP, UDP	Connection hijacking	TLS, DTLS
Internet	IP, ICMP	Spoofing, fragmentation attacks	IPSec
Link	Ethernet, ARP	MAC spoofing, ARP spoofing	802.1X, ARP inspection

3.2 SSL/TLS (Secure Sockets Layer / Transport Layer Security)

Aspect	Detail
Purpose	Secure communication over TCP (HTTPS, FTPS, SMTPS)
Layers	Record protocol (encryption), Handshake protocol (authentication, key exchange)
TLS versions	TLS 1.2 (widely used), TLS 1.3 (faster, more secure)

TLS Handshake Summary:

Client → Server: ClientHello (supported ciphers, random)
Server → Client: ServerHello (chosen cipher, random, certificate)
Client → Server: Pre-master secret (encrypted with server's public key)
Both: Generate session keys
Client → Server: Finished (encrypted)
Server → Client: Finished

3.3 IPSec (Internet Protocol Security)

Aspect	Detail
Purpose	Secure IP communications (network layer)
Modes	Transport mode (end-to-end), Tunnel mode (gateway-to-gateway)
Protocols	AH (Authentication Header) – integrity, authentication ESP (Encapsulating Security Payload) – confidentiality, integrity, authentication

IPSec Security Associations (SA):

Unidirectional logical connection
Defined by: SPI, destination IP, security protocol
Contains: encryption algorithm, key, authentication method

3.4 SSH (Secure Shell)

Aspect	Detail
Purpose	Secure remote login and command execution
Port	22
Features	Secure file transfer (SFTP), port forwarding, X11 forwarding
Authentication	Password, public key, host-based

3.5 VPN (Virtual Private Network)

Aspect	Detail
Purpose	Extend private network over public internet
Types	Site-to-site, remote access, SSL VPN
Protocols	IPSec, OpenVPN, WireGuard, PPTP (obsolete)

3.6 Email Security

Protocol	Port	Encryption	Authentication
SMTP	25, 587	STARTTLS	None (inherent)
POP3	110, 995	TLS/SSL	Username/password
IMAP	143, 993	TLS/SSL	Username/password

Secure Email Standards:

S/MIME: Uses PKI for encryption and signing
PGP/GPG: Web of trust model for key management

3.7 DNS Security

Threat	Description	Mitigation
DNS spoofing	Poisoning DNS cache	DNSSEC
DNS amplification	DDoS using DNS	Rate limiting
DNS tunneling	Data exfiltration	Deep packet inspection

DNSSEC (DNS Security Extensions):

Adds digital signatures to DNS records
Protects against cache poisoning
Uses RRSIG, DNSKEY, DS records

4. System Security

4.1 Authentication Methods

Factor	Description	Examples
Something you know	Knowledge-based	Password, PIN, passphrase
Something you have	Possession-based	Smart card, token, phone
Something you are	Biometric	Fingerprint, iris, face
Something you do	Behavioral	Signature, typing pattern
Somewhere you are	Location-based	GPS, IP geolocation

4.2 Password Security

Attack Type	Description	Mitigation
Brute force	Try all combinations	Long passwords, rate limiting
Dictionary attack	Try common words	Complex passwords, salting
Rainbow table	Precomputed hash table	Salt (random per password)
Phishing	Fake login pages	2FA, user education

Password Storage Best Practices:

Never store plaintext passwords
Use strong hash (bcrypt, scrypt, Argon2)
Use unique salt per password
Enforce password complexity

4.3 Access Control Models

Model	Principle	Applications
DAC (Discretionary)	Owner controls access	File systems
MAC (Mandatory)	System controls access	Military, government
RBAC (Role-Based)	Access based on roles	Enterprise systems
ABAC (Attribute-Based)	Access based on attributes	Cloud, fine-grained

4.4 Malware

Type	Description	Characteristics
Virus	Attaches to legitimate programs	Requires user execution
Worm	Self-propagates without user action	Spreads over networks
Trojan	Disguised as legitimate software	Requires user deception
Ransomware	Encrypts files for ransom	Demands payment
Spyware	Steals information	Runs silently
Rootkit	Hides presence	Modifies OS
Botnet	Remotely controlled network	DDoS, spam

4.5 Intrusion Detection/Prevention Systems (IDS/IPS)

Type	Location	Action	Examples
NIDS	Network segment	Alert only	Snort, Suricata
NIPS	Inline	Block traffic	Snort inline, Suricata
HIDS	Host	Monitor host activity	OSSEC, Tripwire

Detection Methods:

Signature-based: Matches known attack patterns (fast, misses zero-day)
Anomaly-based: Baseline normal behavior (detects zero-day, higher false positives)
Stateful protocol analysis: Tracks protocol states

4.6 Firewalls

Type	Layer	Description	Examples
Packet filtering	3-4	Examines headers (IP, port)	iptables, ACLs
Stateful inspection	3-4	Tracks connection state	Cisco ASA
Application gateway	7	Proxies specific applications	Web proxy
Next-gen (NGFW)	3-7	Deep packet inspection, IPS	Palo Alto, Fortinet

5. Web Security

5.1 OWASP Top 10 Vulnerabilities (2021)

Rank	Vulnerability	Description
1	Broken Access Control	Unauthorized access to resources
2	Cryptographic Failures	Weak or missing encryption
3	Injection (SQL, XSS, etc.)	Untrusted input executed as code
4	Insecure Design	Design flaws
5	Security Misconfiguration	Default configurations, verbose errors
6	Vulnerable Components	Outdated libraries
7	Identification Failures	Weak session management
8	Software/Data Integrity Failures	Untrusted updates
9	Security Logging Failures	Insufficient monitoring
10	SSRF	Server-side request forgery

5.2 Common Web Attacks

Attack	Description	Mitigation
SQL Injection	Malicious SQL inserted into query	Parameterized queries, input validation
XSS (Cross-Site Scripting)	Malicious script injected into web pages	Output encoding, CSP
CSRF (Cross-Site Request Forgery)	Unauthorized requests from authenticated user	Anti-CSRF tokens, SameSite cookies
Session hijacking	Stealing session tokens	Secure cookies, HTTPS, regenerate session ID
Directory traversal	Accessing files outside web root	Input validation, chroot

SQL Injection Example:

-- Vulnerable code
query = "SELECT * FROM users WHERE username = '" + username + "'"
-- Attack input: ' OR '1'='1
-- Result: SELECT * FROM users WHERE username = '' OR '1'='1'

Prevention: Use parameterized queries/prepared statements

5.3 HTTPS (HTTP over TLS)

Aspect	Detail
Default port	443
Encryption	TLS (formerly SSL)
Certificate	Required from CA
HSTS	Forces HTTPS for all connections

6. Wireless Network Security

6.1 Wi-Fi Security Protocols

Protocol	Encryption	Authentication	Status
WEP	RC4	Pre-shared key	Broken (do not use)
WPA	TKIP (RC4)	PSK or 802.1X	Deprecated
WPA2	CCMP (AES)	PSK or 802.1X	Current (KRACK vulnerability)
WPA3	GCMP-256	SAE	Latest (most secure)

6.2 802.1X (Port-Based Authentication)

Components:

Supplicant: Client device
Authenticator: Switch/AP
Authentication server: RADIUS

6.3 Wireless Attacks

Attack	Description	Mitigation
Evil twin	Fake AP mimicking legitimate	Certificate validation
Deauthentication	Disconnecting clients	802.11w (Management Frame Protection)
KRACK	Key reinstallation attack	WPA3, patched WPA2
Wardriving	Mapping Wi-Fi networks	Disable SSID broadcast (limited value)

7. Cloud Security

7.1 Shared Responsibility Model

Service Model	Provider Responsibility	Customer Responsibility
IaaS	Infrastructure, virtualization	OS, middleware, apps, data
PaaS	Infrastructure, OS, middleware	Apps, data
SaaS	Everything except data	Data, access

7.2 Cloud Security Challenges

Challenge	Description	Mitigation
Data residency	Legal jurisdiction of data	Choose region
Multi-tenancy	Co-mingled data	Encryption, isolation
API security	API as attack surface	Strong authentication, rate limiting
Compliance	Regulatory requirements	Certifications (SOC2, ISO 27001)

8. Sample Exam Questions

Short Answer (5 marks each)

Distinguish between symmetric and asymmetric encryption. Give one example of each.
What is the difference between a virus and a worm?
Explain the purpose of a digital signature. How does it provide non-repudiation?
What is the difference between IDS and IPS?
List the five factors of authentication.

Numerical/Conceptual Problems (10-15 marks)

1. RSA Calculation:
Given p = 11, q = 13, e = 7. Compute n, φ(n), d, and encrypt M = 5.

Solution:

n = p × q = 11 × 13 = 143
φ(n) = (p-1)(q-1) = 10 × 12 = 120
d = e⁻¹ mod φ(n) = 7⁻¹ mod 120
7 × 103 = 721 ≡ 1 mod 120 (since 120×6=720)
d = 103
Encryption: C = M^e mod n = 5⁷ mod 143
5²=25, 5⁴=25²=625≡53, 5⁷=5⁴×5²×5=53×25×5=53×125=6625
6625 mod 143: 143×46=6578, 6625-6578=47
C = 47

2. Diffie-Hellman:
p = 23, g = 5. Alice chooses a = 6, Bob chooses b = 15. Compute A, B, and shared secret K.

Solution:

A = g^a mod p = 5⁶ mod 23
5²=25≡2, 5⁴≡4, 5⁶=5⁴×5²≡4×2=8 mod 23
B = g^b mod p = 5¹⁵ mod 23
5⁸=5⁴×5⁴≡4×4=16, 5¹⁵=5⁸×5⁴×5²×5≡16×4×2×5=16×40=640
640 mod 23: 23×27=621, 640-621=19
K = B^a mod p = 19⁶ mod 23
19²=361≡16 (23×15=345, 361-345=16)
19⁴=16²=256≡3 (23×11=253, 256-253=3)
19⁶=19⁴×19²≡3×16=48≡2 (23×2=46, 48-46=2)
K = 2

Quick Revision Table – Cryptographic Algorithms

Algorithm	Type	Key Size	Block Size	Security Status
AES	Symmetric	128/192/256	128 bits	Secure
DES	Symmetric	56	64 bits	Insecure
3DES	Symmetric	112/168	64 bits	Acceptable (slow)
RSA	Asymmetric	1024-4096	Variable	Secure (≥2048 bits)
ECC	Asymmetric	160-512	Variable	Secure
MD5	Hash	–	128 bits	Broken
SHA-1	Hash	–	160 bits	Weak (deprecated)
SHA-256	Hash	–	256 bits	Secure

Quick Revision Table – Common Ports

Port	Protocol	Service	Security
20,21	FTP	File Transfer	Plaintext (use SFTP)
22	SSH	Secure Shell	Secure
23	Telnet	Remote Login	Insecure
25	SMTP	Email Sending	Plaintext (use STARTTLS)
53	DNS	Domain Resolution	Plaintext (DNSSEC)
80	HTTP	Web	Plaintext (use HTTPS)
110	POP3	Email Retrieval	Plaintext (use POP3S)
143	IMAP	Email Retrieval	Plaintext (use IMAPS)
443	HTTPS	Secure Web	Secure
465	SMTPS	Secure Email	Secure
993	IMAPS	Secure Email	Secure
995	POP3S	Secure Email	Secure