The metal oxide semiconductor FET (MOSFET) is a four-terminal device. Terminals are *source (S), gate (G),* and *drain (D)* . The *substrate* or *body* forms the fourth terminal. The MOSFET is constructed with the channel insulated gate terminal with a silicon dioxide dielectric. MOSFETs can be *exhaustion* or *enhancement mode*

MOSFETs are sometimes called IGFETs (Insulated Gate Field Effect Transistors) because of the SiO _{2} Layer used as an insulator between the gate and the substrate. We start our analysis with the MOSFET in exhaustion mode. Just as BJTs can be *npn* or *PNP* , MOSFETs can be either *n-* channel (NMOS) or *p-* channel (PMOS). Figure 1 illustrates the physical structure and symbol of a channel depletion *n* MOSFET. Notice that the substrate is connected to the originating terminal. This will almost always be the case.

The exhaustion MOSFET is built with a *physical books* Channel inserted between the drain and the source. As a result, when a voltage, *v _{DS}* , is applied between drain and source, a current,

*i*exists between drain and source even though gate terminal G remains disconnected (

_{D},*v*= 0 V).

_{GS}Construction of the *n* -channel MOSFET depletion begins with *p* silicone doped. The *n* Doping source and drain wells form low resistance connections between the *n-* channel ends , as shown in Figure 1. A thin layer of silicon dioxide is deposited covering the area between the source and the sewer system. Sio _{2} is an insulator. A layer of aluminum is deposited on the silicon dioxide insulator to form the door terminal. In operation, a negative. *v _{GS}* pushes electrons out of the channel region, thus depleting the channel. When

*v*reaches a certain voltage,

_{GS}*V*, the channel is

_{T}*pinched*. Positive values of

*v*increase the size of the channel, resulting in an increase in the drain current. The exhaustion MOSFET can work with positive or negative values of

_{GS}*v*. Since the gate is isolated from the channel, the gate current is negligible (on the order of 10).

_{GS}^{-12}LA).

Figure 2 is comparable to Figure 1 except that we have changed the *n* of channel depletion MOSFET to a *p* channel depletion MOSFET.

The *n* MOSFET channel enhancement is illustrated in Figure 3 along with the circuit symbol. This is the most widely used form of field effect transistor.

The channel enhancement *n* MOSFET differs from the exhaustion MOSFET in not having the thin *n-* layer. It requires a positive voltage between the gate and the source to establish a channel. This channel is formed by the action of a positive gate-to-source voltage, *v _{GS}* , that attracts electrons from the substrate region between the

*n*doped drain and the source. Positive

*v*causes electrons to accumulate on the surface below the oxide layer. When the voltage reaches a threshold,

_{GS}*V*, this region attracts a sufficient number of electrons to act as an

_{T}*n-*channel conductor . No appreciable drain current,

*i*exists to

_{D}*v*exceeds

_{GS}*V*.

_{T}Figure 4 is comparable to Figure 3, except that we have changed the *n* channel enhancement MOSFET to a *p* channel enhancement MOSFET.

In summary, the MOSFET family exhibits the identification *i _{D}* vs.

*v*The curves are shown in Figure 5. Each characteristic curve is developed with sufficient drain source voltage

_{GS}*v*to keep the device in the normal operating region of the

_{DS }*i*vs.

_{D}*v*curves. Discussion in later sections will define the voltage threshold.

_{DS}*V*both enhancement MOSFETs and exhaustion MOSFETs.

_{T For}**Features of the MOSFET terminal in upgrade mode 2.1**

**Features of the MOSFET terminal in upgrade mode 2.1**

Now that we have presented the basic structure and bases for MOSFET operation, we use an approach to examine the behavior of the device terminal in upgrade mode. Let’s first make some general observations of Figure 1. Think of the normal flow of current in the MOSFET as from the drain to the source (as in the BJT, it is between the collector and the emitter). As with the *npn* BJT, there are two consecutive diodes between the drain and the source. Therefore, we must apply external voltages to the gate to allow current to flow between the drain and the source.

If we ground the source and apply a positive voltage to the gate, that voltage is effectively the gate-to-source voltage. The positive gate voltage attracts electrons and repels holes. When the voltage exceeds the threshold ( *V _{T}* ), enough electrons are attracted to form a conductive channel between the drain and the source. At this point, the transistor turns on and the current is a function of both

*v*and

_{GS}*v*. It should be clear that

_{DS}*V*is a positive number for an

_{T}*n*channel device, and a negative number for a

*p*channel device.

Once a channel is created (i.e. *v _{GS }*>

*V*), current flow can occur in that channel between the drain and the source. This current flow depends on

_{T}*v*, but also depends on

_{DS}*v*. When

_{GS}*v*barely exceeds the threshold voltage, very little current can flow. As

_{GS}*v*increases beyond the threshold, the channel contains more carriers and higher currents are possible. Figure 6 shows the relationship between

_{GS}*i*and

_{D}*v*where

_{DS}*v*is a parameter. Note that for

_{GS}*v*Less than the threshold, there are no current flows. For greater

_{GS}*v*, the relationship between

_{GS}*i*and

_{D}*v*is approximately linear, indicating that the MOSFET behaves as a resistance whose resistance depends on

_{DS}*v*.

_{GS}The curves in figure 6 look like straight lines. However, they will not continue as straight lines as *v _{DS}* becomes larger. Remember that a positive gate voltage is used to create the conduit channel. It does this by attracting electrons. The positive drain voltage is doing the same. As we get closer to the drain end of the channel, the voltage creating the channel approaches

*v*–

_{GS}*v*as the two sources oppose each other. When this difference is less than

_{DS}*V*, the channel no longer exists for the entire space between the source and the drain. The channel is

_{T}*constricted*at the end of the drain, and further increases in

*v*does not lead to any increase in

_{DS}*i*. This is known as the normal operating region or

_{D}*saturation*region shown in Figure 7 by the horizontal section of the characteristic curves. When the difference is greater than

*V*, we call this theMode

_{T}*triode*, because the potentials at all three terminals strongly affect the current.

The preceding discussion leads to the operating curves of Figure 7.

The transition between the triod and the normal operating region (called the saturation region and often identified as pinch mode operation) is shown as the dashed line in Figure 7, where

(one)

At the edge of the triode region, the knees of the curves roughly follow the relationship,

(2)

In equation (2), K is a constant for a given device. Its value depends on the dimensions of the device and the materials used in its construction. The constant is given by,

(3)

In this equation, *μ _{n}* is the mobility of the electron;

*C*, the

_{oxide}*capacitance, is the capacitance per unit area of the gate;*

_{oxide}*W*is the width of the door;

*L*is the length of the gate. The equation indicates a complicated, nonlinear relationship between

*i*and the two voltages,

_{D}*v*and

_{DS}*v*. Since we would like the drain current to vary approximately linearly with

_{GS}*v*(independent of

_{GS}*v*), FET is generally not used in the triode region.

_{DS}Now we want to find an equation for the operation curves in the saturation region. We can establish the values at the transition between the triode and the saturation region by evaluating Equation (2) at the transition (knee). That is to say,

(4)

This equation establishes the magnitude of the drain current at the limit (dashed line in Figure 8) as a function of the gate-to-source voltage *v _{GS}* . If necessary, we can explain the slight slope of the characteristic curves in the saturation region by adding a linear factor.

(5)

In equation (5), *λ* is a small constant (the slope of the nearly horizontal section of the characteristic curves shown in Figure 8). It is usually less than 0.001 (V ^{-1} ). So

(6)

All of our previous discussion was about the NMOS transistor. We now briefly discuss the necessary modifications for PMOS. For PMOS, the values of *v _{DS}* will be negative Additionally, to create a channel PMOS

The only change in the characteristics of NMOS transistors (Figure 7) is that the horizontal axis is now -v _{DS }instead of + v _{DS,} and the parametric curves represent a higher drain current as the gate voltage decreases. (instead of increasing for the NMOS transistor). The curves to increase the current values correspond to a more negative gate voltage. When *v _{GS }*>

*V*, the transistor is cut. For PMOS improvement,

_{T}*V*is negative, and for PMOS depletion,

_{T}*V*is positive.

_{T}The equation for the triode region transition current for the PMOS transistor is identical to that for NMOS. That is to say,

(7)

Note that *v _{GS}* and

*v*are both negative quantities. The equation for the saturation region in the PMOS transistor is also identical to that for NMOS. That is to say,

_{DS}

(8)

Note that *λ* is negative for PMOS transistors since the rate of change of curve (

Taking the partial derivative of both sides of equation (6) with respect to *v _{GS}* ,

(9)

We prefer the value of *g _{m}* to be constant, especially for large signal oscillations. However, we can only approach this condition if we use the FET for small signal applications. For large signal conditions, distortion of the waveform may be unacceptable in some applications.

**Exhaustion Mode MOSFET 2.2**

**Exhaustion Mode MOSFET 2.2**

The previous section deals with the enhancement MOSFET mode. Now we contrast this with the MOSFET in exhaustion mode. For the *n* -channel upgrade mode, to acquire a channel we had to apply a positive voltage to the gate. This voltage had to be large enough to force a sufficient number of moving electrons to produce a current in an induced channel.

In the section that puts *n* -MOSFET in channel exhaustion mode, we don’t need this positive voltage since we have a physically implanted channel. This allows us to have current between the drain and source terminals, even with negative voltages applied to the gate. Of course, there is a limit to the amount of negative voltage that can be applied to the gate while maintaining current flow between the drain and the source. This limit is identified again as the threshold voltage, *V _{T}* . The change in upgrade mode is that the gate-to-source voltage can now be negative or positive, as shown in Figure 9.

The equations that define how the MOSFET works in exhaustion mode are very similar to those in enhancement mode. The drain current value when *v _{GS}* is zero is identified as

*I*. This is often referred to as the

_{DSS}*drain source saturation current*, or the

*zero – gate drain current*. When comparing the MOSFET equations in enhancement mode with those of exhaustion mode, we found

(10)

Then we find

(eleven)

Exhaustion mode MOSFETs are available discretely, or can be manufactured on integrated circuit chips along with upgrade mode types. This includes both *p* -type and *n* -type. This allows for greater flexibility in circuit design techniques.

**2.3 ****Large Signal Equivalent Circuit**

**2.3**

**Large Signal Equivalent Circuit**Now we want to develop an equivalent circuit that represents the large signal characteristics of Figure 8 [Equation (5) or (8)] in the saturation region. Note that the drain current, *i _{D}* , depends on

*v*and

_{GS}*v*. For a constant gate-to-source voltage, we operate along one of the parametric curves in the figure, and the relationship is approximately a straight line. A straight line relationship between current and voltage is modeled by a resistance. Therefore, the equivalent circuit consists of a resistance in parallel with the current source where the value of the current source sets the portion of the drain current due to

_{DS}*v*. The slope of the curve depends on

_{GS}*v*. The slope is the partial derivative,

_{GS}

(12)

where *r _{0}* is the incremental output resistance. We see in equation [(5) or (8)] that this resistance is given by

(13)

where we use capital letters *V _{GS}* to indicate that resistance is defined for a particular constant value of gate-to-source voltage. The final approximation in equation (13) results from equation (5) with the assumption that

*λ*is small. Resistance is therefore inversely proportional to the bias current

*I*. The equivalent large signal model is shown in Figure 11, where

_{D}*r*is as developed in equation (13).

_{0}**2.4 ****MOSFET Small Signal Model**

**2.4**

**MOSFET Small Signal Model**Now we want to see the incremental effects related to the equation. The three circuit parameters in that equation, *i _{D}* ,

*v*and

_{GS,}*v*are made up of both

_{DS}*dc*(bias) and

*ac*components (which is why we have used uppercase subscripts in expressions). We are interested in

*ac*Components for the small signal model. We see that the drain current depends on two voltages, the gate to the source and the drain to the source. For incremental values, we can write this relationship as

(14)

In equation (14), *g _{m}* is

*the forward transconductance*and

*r*is the output resistance. Their values are found by taking partial derivatives in equation (5). So,

_{0}

(15)

The approximation in equation (15) results from the observation that *λ* is small. Equation (14) leads to the small signal model in Figure 12.