Recent interest by both Google and AMD in TSMC’s SoiC technology has sparked curiosity about what we might see in the future using this new way of building an integrated circuit. What secrets does TSMC’s SoIC technology hide? Are we going to see it implemented in our PCs or is it something that is going to be out of our reach?
One of the fronts that has been investigated more in recent years is in the development of packaging systems that go beyond the conventional model, based on a monolithic chip. A recent example is TSMC’s SoIC , which has attracted the interest of Google and AMD separately.
What is TSMC SoIC packaging?
In reality, the SoiC is nothing more than the interconnection that communicates two chips of a 3D integrated circuit , where the idea of TSMC is to increase the number of connections beyond those used in this type of designs in a conventional way.
The reason? Increasing the number of connections means that less clock speed is required to reach a given clock speed, which translates into much lower energy consumption per transmitted bit of information.
To understand this, we must bear in mind that doubling the clock speed of an interface is four times its consumption, so it is extremely important to be able to create communication interfaces with a large number of pins.
What are 3DIC chips?
It is called 3DIC to those integrated circuits made up of several chips but that are not found on the same level but on several different ones, so instead of being mounted on a huge monolithic chip horizontally, it is mounted on several smaller chips vertically making use for the interconnection of vias that pass through the silicon of the processors.
This has a series of advantages, first of all smaller pieces can be built and that reach a greater number of chips per wafer . secondly, vertical connectivity increases the number of possible connections , which allows us to completely reduce the transfer clock speed for each pin and thus achieve a much lower energy consumption.
So far we have seen memory-based 3DIC constructs, either in memories like the HBM as well as 3D NAND memory, but the next step is to combine logic and memory in a 3DIC configuration or combine multiple pieces of logic together.
The current challenge is not in the speed of calculation but in the transfer of data
One of the problems that engineers face today when designing new systems is not how many operations per cycle and / or instructions a design can achieve, but whether the design has enough data logistics to operate at a fixed energy consumption ratios.
The development of technologies based on communication through silicon pathways, TSV, began a decade ago and the key objective is to always increase the bandwidth, the amount of data transmitted, while maintaining average energy consumption.
The only way to build chiplet-based processors , whether in 3DIC or 2DIC configurations scattered in an interposer, is to make sure to build communication interfaces that meet these energy requirements and the simplest evolution is to increase the number of interfaces to be able to thus reduce energy consumption for a given bandwidth
When we talk about data transmission we are not referring only to communication with the external memory, but also in the case of dividing a chip into several different chiplets, it must be ensured that the energy consumption of the wiring does not skyrocket when transmitting. the same volume of data , since the counterpart to this is that the communication routes are longer, increasing energy consumption considerably.
SoiC packaging types
In the first place we have the CoWoS configurations , which are usually 2..5DIC configurations, so called due to the fact that they usually integrate a monolithic chip connected to an interposer that serves as routing to access 3DIC memory, usually HBM.
These types of configurations have not been very successful in the domestic market due to their high manufacturing cost, but they are used in the high-performance computing market , where the recently introduced AMD CDNAs use this configuration, also the NVIDIA A100 and some Google Tensor Processor Unit settings.
In second place we have the InFO-POP packages and with them we do not go to the other extreme, since they are configurations that are used in the market for smartphones and other PostPC devices , the fact of talking about SoCs for smartphones that are actually 3DICs composed of several different chips opens the door to strange customizations and a new way to take advantage of the limited space of SoCs for Post-PC devices.
Whatever the type of packaging, what TSMC tries to show us is that it is possible to convert a monolithic SoC into a 3DIC that uses SoIC interconnects, although TSMC has not talked about it, it opens the possibility to CPUs and GPUs in conventional sockets and form factors that use SoIC technology, but this is something that TSMC has not announced yet, although it is a possibility.
