Enhance your academic journey with valuable study notes for a BSC in Electrical Engineering at CECOS University, Peshawar. Stay organized, participate actively, and seek support to excel in your studies.By following these study notes and tips, you can maximize your learning experience and succeed in your BSC program in Electrical Engineering at CECOS University, Peshawar. Remember to stay focused, stay curious, and stay committed to your academic and professional development. Good luck on your journey to becoming a successful electrical engineer!

Study Notes BSC in Electrical Engineering at CECOS University, Peshawar.

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ELECTRICAL WORKSHOP PRACTICE – Complete Study Notes

PART 1: WORKSHOP SAFETY

1.1 General Safety Rules

Golden Rules of Electrical Workshop Safety:

1.2 Types of Electrical Hazards

Current Levels and Human Effects (at 60 Hz, path hand-to-hand):

1.3 Personal Protective Equipment (PPE)

PART 2: HAND TOOLS FOR ELECTRICAL WORK

2.1 Cutting and Stripping Tools

2.2 Gripping and Turning Tools

2.3 Bending and Forming Tools

2.4 Measuring and Layout Tools

2.5 Soldering Tools

PART 3: CONDUIT AND RACEWAY INSTALLATION

3.1 Types of Conduit

3.2 Hand Bending EMT (30°, 45°, 90°)

The 90° Stub-up Bending Procedure:

Example (90° stub for 1/2″ EMT, stub height 18″):

• Deduct for 1/2″ EMT = 5″

• Mark conduit at 18″ – 5″ = 13″ from end

• Insert conduit with mark at arrow; bend to 90°

Offset Bending (Three-Point Saddle or Four-Bend Saddle):

For a 30° offset:

• Bend at mark 1 (first bend angle = 30°)

• Distance between bends = offset height × 2

• Bend at mark 2 (second bend opposite direction, 30°)

Example (2″ offset with 30° bends):

• Distance between bends = 2″ × 2 = 4″

• Mark both points; bend 30° at each mark in opposite directions

3.3 Box Fill Calculations (NEC 314.16)

Rule: Each conductor, device, and fitting occupies a specific volume; total cannot exceed box volume.

Example (Box fill for 3 #12 conductors + 1 receptacle + grounds):

• Conductors: 3 × 2.25 = 6.75 in³

• Receptacle: 2 × 2.25 = 4.5 in³

• Grounds: 1 × 2.25 = 2.25 in³ (total grounds = 1 allowance)

• Total = 13.5 in³ needed → Use 18 in³ box minimum

PART 4: WIRING AND CABLE INSTALLATION

4.1 Types of Wiring

4.2 Wire Stripping Procedure

Step-by-step (using automatic or manual stripper):

Common Error: Nicking the copper conductor creates a weak point that can break under load or cause heating.

4.3 Making Wire Connections

Twisting Wires for Wire Nuts (WingTwist):

Never pre-twist with pliers? Some manufacturers recommend against pre-twisting (like Ideal). Follow specific manufacturer instructions. Many electricians strip to proper length, hold wires parallel, and screw wire nut on (which twists the wires and nut together).

Terminal Connections (Receptacles and Switches):

Hook method rule: The hook must close around the screw, not open. Clockwise hook (as screw tightens, hook tightens). No open hooks or hooks wrapped backwards.

4.4 Color Coding (NEC Standard)

PART 5: INSTALLATION OF DEVICES

5.1 Receptacle Installation (120V, 15A/20A)

Standard Duplex Receptacle (15A):

Receptacle Orientation: Ground hole up (preferred) reduces risk of short circuit if metal object falls across plug prongs. Some electricians install ground down (common).

Split Receptacle (Switched outlet, half hot, half switched):

• Remove tab on brass side (between upper and lower terminals)

• Top terminal: black (constant hot)

• Bottom terminal: red (switched hot)

• Neutral side: tab remains intact (neutral shared)

• Ground: green screw

5.2 Switch Installation

Three-Way Switch Circuit Diagram:

Power → 3-way (common) ───traveler─── 3-way (common) → Light
                     └───traveler───┘

Marking terminology:

• Common (COM): Dark screw (power in or load out)

• Traveler (Traveler/Straps): Brass screws (carry switching signal between 3-ways)

• Ground: Green screw

5.3 Lighting Fixtures

PART 6: PANELBOARD AND OVERCURRENT PROTECTION

6.1 Main Electrical Panel

Components (Inside Load Center):

Neutral vs. Ground (Critical Distinction):

Reason for isolating neutral in subpanel: Prevents ground loops and ensures ground fault path returns to main panel. Neutral current should NEVER flow on ground wire.

6.2 Circuit Breaker Types

GFCI Protection Requirement (NEC 210.8):

• Bathrooms, garages, outdoors, crawl spaces, unfinished basements, kitchen countertops (within 6′ of sink), laundry areas

6.3 Circuit Sizing and Wire Ampacity

Standard branch circuit sizes for residential:

Ampacity Derating Factors (NEC Table 310.15(B)(3)(a)):

Ambient Temperature Correction Factors:

• Hot attic or rooftop: may require larger wire or derate per NEC tables.

PART 7: MEASUREMENT AND TESTING

7.1 Multimeter (Volt-Ohm-Milliammeter)

Basic Functions:

Voltage Measurement:

• Line-to-neutral (Hot to neutral): 120V ±5% typical

• Line-to-line (Hot to hot): 208V (3-phase) or 240V (split single phase)

• Neutral-to-ground (on load, minimal): Usually <5V (0-2V ideal). Higher voltage indicates a problem (shared neutral issues or failing connection).

Resistance Measurement (For Motor Windings, Heating Elements):

7.2 Non-Contact Voltage Tester

Principle: Detects electric field around energized conductors.

Limitations:

• NOT reliable for detecting voltage on shielded cable (MC, AC, BX)

• May give false positive (ghost voltage) on long unconnected wires

• Will NOT detect voltage on neutral (return path) under load (since hot and neutral cancel fields)

• Never use to prove absence of voltage without additional testing

Correct usage:

1. Test on known live source (outlet with light)

2. Test unknown conductor

3. Test known live source again (verifies tester still functional)

7.3 Wire Tracers (Signal Tracer / Toner)

Use: Tracing a wire inside walls or conduit without visual access.

Best for: Finding breakers for unlabeled circuits; identifying wires in crowded panels.

7.4 Clamp Meter (Current Measurement)

Rule: Clamp around ONE conductor only. Clamping around hot + neutral = current cancels → reads 0A.

Inrush Current Measurement (Motors, Transformers, Capacitors):

• Set meter to “Inrush” mode and clamp around hot wire.

• Read peak starting current (can be 5-10× running current).

PART 8: ELECTRIC MOTORS AND MACHINES (WORKSHOP SETTING)

8.1 Types of Motors Used in Workshop

8.2 Motor Overload Protection

Two methods:

Rule: Motor overload protection trips at >115% of FLA (full load amps) for 1 hour or more (for motors with service factor 1.15).

Why not use branch circuit breaker alone for overload: Circuit breaker sized for short circuit and ground fault (by code 250% of FLA for inverse time breaker), cannot protect motor from prolonged overload without nuisance trip under starting current.

8.3 Reversing Motor Rotation

Warning: Verify with motor wiring diagram. Incorrect swapping may not reverse (single-phase) or may cause hazardous rotation direction (three-phase).

PART 9: GROUNDING AND BONDING

9.1 Key Definitions (NEC Article 100)

9.2 Grounding Electrode System (NEC 250.50)

Required electrodes (all present must be bonded together to form grounding electrode system):

Grounding Electrode Conductor (GEC): Size based on largest service entrance conductor (NEC Table 250.66).

Example (200A residential service, copper conductors):

• Largest service entrance conductor size: 2/0 AWG copper typical

• Minimum GEC to ground rod: #6 AWG copper (or #4? Check Table 250.66: for 2/0 copper, GEC = #4 copper)

• Ground rod clamp (acorn) required for each rod

PART 10: RESIDENTIAL WIRING EXAMPLES

10.1 Basic Lighting Circuit (15A, #14 AWG)

Components:

• 15A single-pole breaker

• #14/2 with ground NM-B (Romex)

• Single-pole switch(es)

• Light fixture

Flow: Breaker → switch (hot) → fixture → neutral back to panel

10.2 Receptacle (Outlet) Circuit

General purpose (NEC 210.52):

• Spacing: No point along floor line > 6 ft from receptacle (so receptacles every 12 ft)

• Wall space > 2 ft wide requires receptacle

Kitchen small appliance circuits (NEC 210.52(B)):

• Two 20A circuits minimum (#12 AWG)

• Serve all countertop receptacles (GFCI protected)

• No other outlets (lights, disposals) on these two circuits

10.3 Dryer Circuit (30A, 240V, 4-wire)

• Breaker: 30A two-pole

• Wire: #10/3 with ground (4 conductors: L1 black, L2 red, neutral white, ground bare/green)

• Receptacle: 14-30R (4-wire)

• Range/Dryer 4-wire requirement since 1996 NEC (separate neutral and ground bond in appliance not at receptacle)

SAMPLE EXAM QUESTIONS

Question 1 (Safety)

List five general safety rules for working in an electrical workshop.

Model Answer:

1. Treat all circuits as LIVE until proven dead; always test before touching.

2. Use proper lockout/tagout procedure when working on equipment that could be energized.

3. Wear appropriate PPE including safety glasses, insulated gloves, and safety shoes.

4. Keep work area clean and dry; use insulated mats when necessary.

5. Never work alone on high-voltage systems; have a second person who can cut power and perform rescue.

Question 2 (Conduit Bending)

You need to bend a 90° stub in 3/4″ EMT with a stub height of 24 inches. The deduct for 3/4″ EMT is 6 inches. Where do you mark the conduit?

Model Answer:

• Stub height = 24 inches

• Deduct = 6 inches

• Mark location = 24″ – 6″ = 18 inches from end of conduit

• Insert conduit in bender with mark aligned with arrow on bender

• Bend to 90°; check with level; verify stub height

Question 3 (Box Fill)

A metal box contains four #12 AWG conductors (two incoming, two outgoing), one receptacle, one internal cable clamp (for NM cable entry), and ground wires. Calculate the required box volume.

Model Answer (Using NEC box fill rules, #12 = 2.25 in³ each):

• Conductors: 4 × 2.25 = 9.00 in³

• Receptacle: 2 × 2.25 = 4.50 in³

• Internal clamp: 1 × 2.25 = 2.25 in³

• Ground wires: 1 × 2.25 = 2.25 in³

• Total required volume = 9.00 + 4.50 + 2.25 + 2.25 = 18.0 in³

• Minimum box size: 18 in³ (e.g., 4″ × 4″ × 1.5″ square box = 24 in³, acceptable)

Question 4 (Motor Overload)

A 5 HP, 230V single-phase motor has a nameplate full load current (FLA) of 28 A. What size inverse-time circuit breaker is permitted for short-circuit and ground-fault protection (maximum)? What size overload heater is required?

Model Answer (NEC Table 430.248 for FLA, Table 430.52 for breaker sizing):

• Table 430.248: 5 HP, 230V single-phase FLA = 28 A.

• Breaker sizing (inverse time) = 250% of FLA = 28 × 2.5 = 70 A (maximum permitted).

• Overload protection (heaters) sized at 115% of nameplate FLA = 28 × 1.15 = 32.2 A → Select 32 A heater class (or nearest available not exceeding 125% of FLA if motor service factor < 1.15 — in practice, match motor manufacturer’s overload selection table).

QUICK REFERENCE TABLES

Wire Ampacity (Copper, 60°C/75°C, NEC Table 310.16)

Conduit Fill (Maximum number of THHN/THWN #12 conductors, EMT, 40% fill)

Color Code (AC Power, Phase Identification)

Electrical Network Analysis – Complete Study Notes

Course Overview

Electrical Network Analysis is the foundation of electrical engineering. It provides the mathematical and conceptual tools to determine voltages and currents in any electrical circuit, whether simple resistors or complex AC networks. This course covers DC and AC circuit behavior, network theorems, transient analysis, and resonance.

Core Question: Given an electrical network (components + connections), how do we predict voltages at every node and currents through every branch?

Prerequisites: Basic physics (electricity and magnetism), differential equations, complex numbers, and matrix algebra.

PART 1: FUNDAMENTAL CONCEPTS

1.1 Basic Electrical Quantities

Passive Sign Convention: Power is absorbed (positive) when current enters the positive terminal of an element. Power is delivered (negative) when current leaves the positive terminal.

1.2 Ideal Basic Circuit Elements

Types of Dependent Sources:

1.3 Ohm’s Law

Fundamental relationship for resistors:

v = iR  or  i = Gv  where G = 1/R (conductance, siemens S)

PART 2: DC NETWORK ANALYSIS

2.1 Kirchhoff’s Laws

Kirchhoff’s Current Law (KCL): The algebraic sum of currents entering a node is zero.

Σ i_in = Σ i_out    or    Σ i = 0 at any node

Kirchhoff’s Voltage Law (KVL): The algebraic sum of voltages around any closed loop is zero.

Σ v = 0 around any closed loop

Sign Convention for KVL:

• Going from (-) to (+) through a voltage source: +V (voltage rise)

• Going from (+) to (-) through a voltage source: -V (voltage drop)

• For a resistor, voltage drop = +iR when going with current direction, -iR when going against current direction.

2.2 Series and Parallel Combinations

Resistors in Series:

R_eq = R₁ + R₂ + ... + R_n

• Same current through all

• Voltage divides proportionally to resistance

Resistors in Parallel:

1/R_eq = 1/R₁ + 1/R₂ + ... + 1/R_n    or    G_eq = G₁ + G₂ + ... + G_n

• Same voltage across all

• Current divides inversely proportional to resistance

Special Case (Two Resistors in Parallel):

R_eq = (R₁ × R₂) / (R₁ + R₂)

Inductors in Series: L_eq = L₁ + L₂ + … + L_n

Inductors in Parallel: 1/L_eq = 1/L₁ + 1/L₂ + … + 1/L_n

Capacitors in Parallel: C_eq = C₁ + C₂ + … + C_n

Capacitors in Series: 1/C_eq = 1/C₁ + 1/C₂ + … + 1/C_n

2.3 Voltage and Current Division

Voltage Divider (series resistors):

v_x = v_total × (R_x / R_total)

• v_x = voltage across resistor R_x

• v_total = total voltage across series combination

• R_total = sum of all resistors in series

Current Divider (parallel resistors):

i_x = i_total × (G_x / G_total) = i_total × (R_total / R_x)

• i_x = current through resistor R_x

• i_total = total current entering parallel combination

Two-Resistor Current Divider (parallel):

i₁ = i_total × R₂ / (R₁ + R₂)
i₂ = i_total × R₁ / (R₁ + R₂)

(The larger resistor gets smaller current)

2.4 Node Voltage Method (Nodal Analysis)

Procedure:

1. Select a reference node (ground), assign voltage = 0

2. Label remaining nodes (N-1 nodes, N = total nodes including reference)

3. Apply KCL at each non-reference node

4. Express currents in terms of node voltages using Ohm’s law

5. Solve resulting system of linear equations

Example:
For a node connected to resistors R₁, R₂, R₃ and a current source I_s:

(v - v₁)/R₁ + (v - v₂)/R₂ + (v - v₃)/R₃ = I_s  (if I_s enters node)

where vₖ are neighboring node voltages.

Supernode: A supernode is formed when a voltage source connects two non-reference nodes. Treat both nodes and the source as a single node for KCL, then add constraint equation v₁ – v₂ = V_source.

2.5 Mesh Current Method (Loop Analysis)

Procedure:

1. Identify meshes (independent loops that do not enclose any other loops)

2. Assign mesh current (clockwise) to each mesh

3. Apply KVL around each mesh

4. Express voltages in terms of mesh currents using Ohm’s law

5. Solve resulting system of linear equations

Mesh vs. Nodal:

Supermesh: A supermesh is formed when a current source appears between two meshes. Exclude the current source and its branch from KVL around the supermesh, then add constraint equation relating the two mesh currents to the source value.

2.6 Source Transformation

Definition: A voltage source in series with a resistor can be replaced by a current source in parallel with the same resistor, and vice versa.

When to use: To simplify circuits for analysis (especially useful before applying Thevenin/Norton and for reducing complexity in large networks).

Limitation: Sources must be ideal (no internal resistance beyond the stated series/parallel resistance). The resistor R must be present (cannot be transformed if R = 0 or R = ∞ unless a limiting process is considered).

PART 3: NETWORK THEOREMS

3.1 Superposition Theorem

Statement: In a linear circuit with multiple independent sources, the voltage or current at any element is the algebraic sum of the contributions of each independent source acting alone.

Procedure:

1. Deactivate all independent sources except one

   • Voltage sources: replace with short circuit (V=0)

   • Current sources: replace with open circuit (I=0)

2. Compute desired quantity due to that source

3. Repeat for each independent source

4. Algebraic sum of contributions

Limitations:

• Applies only to linear circuits (R, L, C, linear dependent sources)

• Does not reduce computational effort for complex circuits (each source requires full circuit solution; superposition is easier when source combinations are simpler, but may require solving many circuits)

• Power (nonlinear) cannot be superimposed directly; must compute current/voltage first, then compute power.

3.2 Thevenin’s Theorem

Statement: Any linear two-terminal network can be replaced by an equivalent circuit consisting of a single voltage source (V_th) in series with a single resistor (R_th).

Finding V_th: Open-circuit voltage across the terminals (with load removed).

Finding R_th:

• Method 1 (for networks with independent sources only): Deactivate independent sources (short voltage sources, open current sources). Compute equivalent resistance seen from terminals.

• Method 2 (networks with dependent and independent sources): Apply a test voltage source (1V) or test current source (1A) at terminals after deactivating independent sources. Dependent sources remain active. R_th = v_test / i_test.

• Method 3 (short-circuit current method): R_th = V_oc / I_sc (where I_sc is short-circuit current across terminals). This works for any network (including dependent sources) and can be computationally easier if both V_oc and I_sc are easy to find.

Thevenin Equivalent Circuit:

        R_th
    +---/\/\/---+---+
    |           |   |
    V_th       Terminals
    |               |
    +---------------+---+

3.3 Norton’s Theorem

Statement: Any linear two-terminal network can be replaced by an equivalent circuit consisting of a single current source (I_N) in parallel with a single resistor (R_N).

Relationship:

I_N = I_sc (short-circuit current at terminals)
R_N = R_th (same as Thevenin resistance)
V_th = I_N × R_N

Norton Equivalent Circuit:

    +---Terminals---+
    |               |
    |  I_N     R_N  |
    |   +----/\/\/--+
    |   |           |
    +---+-----------+

3.4 Maximum Power Transfer Theorem

Statement (Thevenin form): Maximum power is transferred from a source to a load when the load resistance equals the source resistance (R_L = R_th).

Maximum Power Formula:

P_max = V_th² / (4R_th)   =   (I_N² × R_th) / 4

For AC circuits (later section): Maximum power transfer occurs when load impedance is the complex conjugate of source impedance: Z_L = Z_th* (i.e., R_L = R_th and X_L = -X_th).

Applicability:

• Applies to power delivered to R_L, not to overall efficiency (efficiency is 50% at maximum power transfer, which may be very inefficient for power generation; for power transmission, we want high efficiency, so we make load much larger than source impedance – but then we need to match for maximum power? No: in power distribution, we match impedances to avoid reflections and for maximum power transfer (transmission lines require impedance matching for signal power; for 60 Hz AC distribution, we do not match load to source impedance because source impedance is very small, so voltage drop is low, efficiency is high). Communication circuits aim for maximum signal power (matched impedance). Power distribution aims for efficiency (R_L >> R_th).

3.5 Millman’s Theorem

Statement: The voltage at the common node of several parallel branches (each consisting of a voltage source in series with a resistor) is:

v = (Σ (V_k / R_k)) / (Σ (1/R_k))

where the sum is over all branches connected to the node (with appropriate sign for V_k orientation).

Special case with current sources: Replace each current source I_k in parallel with R_k as V_k = I_k R_k in series with R_k using source transformation, then apply Millman’s formula.

Application: Finding voltage at a single node when multiple branches connect to it (simpler than nodal analysis if multiple sources are present in parallel).

PART 4: NETWORK TOPOLOGY

4.1 Key Definitions

Graph Theory Relationships:

Number of nodes: n
Number of branches: b
Number of tree branches: t = n - 1
Number of links (cotree branches): l = b - n + 1
Number of fundamental loops: l = b - n + 1
Number of fundamental cut-sets: n - 1

Incidence Matrix (A):

• Rows = nodes, columns = branches (after excluding reference node)

• a_ij = +1 if branch j leaves node i (orientation defined arbitrarily)

• a_ij = -1 if branch j enters node i

• a_ij = 0 if branch j not incident to node i

• Used for systematic circuit formulation (nodal equations via A·i_b = 0, v_b = A^T·v_n)

4.2 Dual Networks

Definition: Two networks are duals if their mesh equations and node equations have the same form, with current and voltage interchanged.

Duality Transformations:

PART 5: SINUSOIDAL STEADY-STATE ANALYSIS (AC)

5.1 Sinusoidal Waveforms

General Form:

v(t) = V_m sin(ωt + θ)   or   v(t) = V_m cos(ωt + φ)

where:

• V_m = peak amplitude (volts)

• ω = 2πf = angular frequency (rad/s)

• f = frequency (Hz)

• θ (phi) = phase angle (radians or degrees)

Period: T = 1/f = 2π/ω

Root Mean Square (RMS) Value:

V_rms = V_m / √2   (for sinusoidal waveform)
I_rms = I_m / √2

Significance: RMS value of an AC waveform equals the DC value that would deliver the same average power to a resistor. For a sinusoidal current i(t) = I_m sin(ωt+θ), P_avg = I_rms² R = (I_m²/2)R.

5.2 Phasor Representation

Definition: A phasor is a complex number representing the magnitude and phase of a sinusoidal quantity. Phasor analysis transforms differential equations into algebraic equations in the frequency domain.

Time Domain ↔ Phasor Domain:

Important: Phasor analysis assumes:

• All sources have the same frequency (if frequencies differ, superposition must be applied in time domain or use the same frequency basis and convert)

• System is linear and in steady state (transients have decayed)

• Phasors represent RMS values in many power engineering contexts, but also peak values. The standard is: use V_pk for phasor magnitude unless stated otherwise. When using RMS, P = V_rms I_rms cosθ (true average power). For peak phasors, P = (V_m I_m/2) cosθ.

5.3 Impedance and Admittance

Impedance (Z): Ratio of phasor voltage to phasor current (complex resistance)

Z = V / I = R + jX

• R = resistance (real part)

• X = reactance (imaginary part)

• |Z| = magnitude = √(R² + X²)

• θ_z = phase angle = arctan(X/R)

Admittance (Y): Reciprocal of impedance

Y = 1/Z = G + jB

• G = conductance (real part)

• B = susceptance (imaginary part)

Impedance of Basic Elements:

Impedance in Series: Z_eq = Z₁ + Z₂ + … + Z_n

Impedance in Parallel: 1/Z_eq = 1/Z₁ + 1/Z₂ + … + 1/Z_n

5.4 AC Power Analysis

Instantaneous Power:

p(t) = v(t) × i(t) = V_m I_m cos(ωt + θ_v) cos(ωt + θ_i)

Average (Real) Power (P):

P = V_rms I_rms cos(θ_v - θ_i) = (V_m I_m / 2) cos(φ)

where φ = θ_v – θ_i = power factor angle (V leads I by φ, I leads V by -φ). Cos φ = power factor (pf).

Reactive Power (Q):

Q = V_rms I_rms sin(φ) = (V_m I_m / 2) sin(φ)

Units: Volt-Ampere Reactive (VAR)

Apparent Power (S):

S = V_rms I_rms = √(P² + Q²)

Units: Volt-Ampere (VA)

Complex Power (S):

S = P + jQ = V_rms I_rms* = V_rms I_rms ∠φ = V·I*

where I* is the complex conjugate of I.

Power Factor, pf = cos φ = P/S = (average power)/(apparent power).

• Leading pf: current leads voltage (capacitive load, φ negative, Q negative)

• Lagging pf: current lags voltage (inductive load, φ positive, Q positive)

Power Triangle:

        S (VA)
        /|
       / |
      /  | Q (VAR)
     / φ |
    /____|
      P (W)

5.5 Resonance in AC Circuits

Series Resonance (RLC in series):

• Resonance occurs when: X_L = X_C ⇒ ωL = 1/(ωC)

• Resonant frequency: ω₀ = 1/√(LC) ; f₀ = 1/(2π√(LC))

• At resonance: Z = R (minimum impedance, maximum current)

• Quality factor (Q) of series RLC: Q = ω₀L/R = 1/(ω₀RC) = (1/R)√(L/C) (also called Q-factor; for a series RLC, Q = (ω₀L)/R)

• Bandwidth (BW): BW = ω₀/Q = R/L (for series RLC)

• Half-power (cutoff) frequencies:
  ω₁,₂ = ω₀ √(1 + 1/(4Q²)) ∓ ω₀/(2Q) (approximate: ω₀ ∓ ω₀/(2Q) if Q is high)

Parallel Resonance (RLC in parallel):

• Resonance occurs when: B_L = B_C ⇒ 1/(ωL) = ωC

• Resonant frequency: same ω₀ = 1/√(LC)

• At resonance: Y = G (minimum admittance, minimum current from source; maximum impedance, maximum voltage across the parallel combination)

• Quality factor (Q) of parallel RLC: Q = R/(ω₀L) = ω₀RC = R√(C/L) (for ideal parallel RLC where resistor is in parallel with L and C; if resistor is in series with inductor, more complex)

• Bandwidth (BW): BW = ω₀/Q = 1/(RC) (for parallel RLC)

• Half-power (cutoff) frequencies: approximate: ω₀ ∓ ω₀/(2Q)

PART 6: TRANSIENT ANALYSIS

6.1 First-Order Circuits (RC and RL)

Natural Response (source-free, no external source; initial condition determines response):

• RC circuit (discharging capacitor via R):
  v(t) = V₀ e^(-t/τ), where τ = RC

• RL circuit (decaying current in inductor):
  i(t) = I₀ e^(-t/τ), where τ = L/R

Step Response (with DC source, single change at t=0):

• RC circuit (charging capacitor via R):
  v_c(t) = V_f + (V₀ – V_f)e^(-t/τ), where V_f = final voltage (source voltage for step input), V₀ = V_c(0⁻) is initial voltage, τ = RC.

• RL circuit (current buildup):
  i_L(t) = I_f + (I₀ – I_f)e^(-t/τ), where I_f = final current (V_source/R when inductor acts as short in steady state DC), I₀ = I_L(0⁻), τ = L/R.

Time Constant (τ = RC or L/R): The time for the response to reach 63.2% of its final change (for an exponential step response: v(t) = V_f + (V₀-V_f)(1 – e^(-t/τ)), the capacitor changes by 63.2% of (V_f-V₀) after one time constant). After 5τ, the response is within 0.67% of final (steady state).

Key Observations:

• Capacitor voltage cannot change instantaneously (v_c(0⁺) = v_c(0⁻))

• Inductor current cannot change instantaneously (i_L(0⁺) = i_L(0⁻))

6.2 Second-Order Circuits (RLC)

Series RLC (source-free):
Kirchhoff’s voltage law around loop: L di/dt + Ri + (1/C)∫ i dt = 0 ⇒ d²i/dt² + (R/L) di/dt + (1/(LC)) i = 0

Characteristic equation: s² + (R/L)s + 1/(LC) = 0

Roots:

s₁,₂ = -α ± √(α² - ω₀²)

where α = R/(2L) (neper frequency, damping coefficient) and ω₀ = 1/√(LC) (undamped resonant frequency)

Damping Cases:

Damped natural frequency: ω_d = √(ω₀² – α²)

Parallel RLC (source-free):
KCL: C dv/dt + v/R + (1/L)∫v dt = 0 ⇒ d²v/dt² + (1/RC) dv/dt + (1/(LC)) v = 0
Here α = 1/(2RC)

Voltage and current relationships for initial conditions:

• For series RLC: i_L(0⁺) = i_L(0⁻); v_c(0⁺) = v_c(0⁻) (use i_L and v_c as state variables)

• The initial conditions yield equations for A₁ and A₂.

Frequency domain approach (Laplace transform) is more systematic for circuits with multiple sources and complex switching sequences. The Laplace transform replaces differential equations with algebraic equations in s-domain. We’ll cover it in PART 7.

PART 7: LAPLACE TRANSFORM IN CIRCUIT ANALYSIS

7.1 Definition

The Laplace transform converts time-domain functions to s-domain functions, turning differential equations into algebraic equations in s.

One-sided Laplace Transform:

F(s) = L{f(t)} = ∫₀⁻^∞ f(t) e^{-st} dt

Common Laplace Transforms:

7.2 Laplace Circuit Models

Transformed Circuit Elements (with initial conditions):

When to use serial or parallel models: Use whichever makes circuit algebra easier. Both are equivalent; they just represent the initial condition as either an initial voltage (series model for C, parallel model for L?) Wait: For inductor, the series model includes an initial voltage source -L i(0⁻). For capacitor, the parallel model includes an initial current source C v(0⁻). But you can also use the alternative with a voltage source in series for the capacitor: V(s) = (1/(sC))I(s) + v(0⁻)/s, and for the inductor: I(s) = (1/(sL))V(s) + i(0⁻)/s. Both are correct; choose for convenience.

7.3 Circuit Analysis in s-Domain

Procedure:

1. Transform circuit to s-domain (include initial conditions as sources)

2. Write equations using KVL, KCL, or Nodal/Mesh in s-domain

3. Solve for desired variable (I(s) or V(s))

4. Perform inverse Laplace transform to obtain time-domain response

PART 8: TWO-PORT NETWORKS

8.1 Definitions and Parameters

A two-port network has two pairs of terminals: input and output. It is characterized by the relationship between voltages (V₁, V₂) and currents (I₁, I₂).

Relationships between Parameters:

• [Y] = [Z]⁻¹ (provided [Z] is invertible)

• [Z] = [Y]⁻¹

• [T_total] = [T₁] × [T₂] for cascaded networks (multiply transmission matrices in order)

Conversion Formulas (Z ↔ Y for 2×2 matrices):

y₁₁ = z₂₂ / Δ_z, y₁₂ = -z₁₂ / Δ_z, y₂₁ = -z₂₁ / Δ_z, y₂₂ = z₁₁ / Δ_z
z₁₁ = y₂₂ / Δ_y, z₁₂ = -y₁₂ / Δ_y, z₂₁ = -y₂₁ / Δ_y, z₂₂ = y₁₁ / Δ_y

where Δ_z = z₁₁ z₂₂ – z₁₂ z₂₁, Δ_y = y₁₁ y₂₂ – y₁₂ y₂₁

Conversion Formulas (Z to H):

h₁₁ = (z₁₁ z₂₂ - z₁₂ z₂₁) / z₂₂ ; h₁₂ = z₁₂ / z₂₂ ; h₂₁ = -z₂₁ / z₂₂ ; h₂₂ = 1 / z₂₂

(and similarly for H to Z, and for both to ABCD, etc.)

PART 9: NETWORK FUNCTIONS AND FREQUENCY RESPONSE

9.1 Transfer Functions

Definition: The ratio of output phasor to input phasor (for sinusoidal steady state) or Laplace-domain output to input (general). For a network function H(s) = V_out(s) / V_in(s) (voltage transfer function) or V_out(s)/I_in(s) (transimpedance), etc.

Poles and Zeros:

• Zeros: s-values where H(s) = 0 (roots of numerator polynomial N(s)=0)

• Poles: s-values where H(s) → ∞ (roots of denominator polynomial D(s)=0)

• Pole locations determine transient response stability:

  • All poles with negative real parts → stable (response decays)

  • Any pole with positive real part → unstable (response grows)

  • Poles on imaginary axis ±jω → sustained oscillation (marginally stable)

  • For left half-plane poles, the farther left (more negative), the faster the decay.

9.2 Bode Plots

Purpose: Plot magnitude (in dB) and phase (in degrees) of transfer function H(jω) vs. logarithmic frequency.

Decibels (dB) for magnitude:

|H|_dB = 20 log₁₀ |H|

(For voltage or current ratio. For power gain, use 10 log₁₀(P_out/P_in).)

Asymptotic Approximations for Basic Factors:

Constructing Bode Plots:

1. Express H(s) in normalized form

2. Identify corner frequencies (ω₀ for each pole/zero)

3. Plot asymptotes

4. Add corrections near corner frequencies (3 dB at ω₀ for single pole/zero; for complex poles, peak depends on ζ)

Gain and Phase Margins (for feedback stability):

• Gain margin: how much gain can increase before instability (at phase = -180°)

• Phase margin: how much phase lag can increase before instability (at gain = 1 (0 dB))

Electronic Devices & Circuits – Comprehensive Study Notes

Unit 1: Semiconductor Fundamentals

1.1 Atomic Structure and Energy Bands

Band gap classification at room temperature:

Common semiconductor band gaps (300 K):

• Silicon (Si): 1.12 eV

• Germanium (Ge): 0.67 eV

• Gallium Arsenide (GaAs): 1.42 eV

1.2 Intrinsic Semiconductors

1.3 Extrinsic Semiconductors (Doping)

Carrier concentrations in equilibrium (law of mass action): n × p = n_i² (at thermal equilibrium)

For n-type (N_D >> N_A): n ≈ N_D; p ≈ n_i² / N_D
For p-type (N_A >> N_D): p ≈ N_A; n ≈ n_i² / N_A

Temperature effect: Intrinsic carrier concentration increases with temperature; above a certain temperature, intrinsic carriers exceed dopant carriers → device failure or degradation of properties.

1.4 Carrier Transport – Drift and Diffusion

Total current density: J_total = J_n(drift) + J_p(drift) + J_n(diffusion) + J_p(diffusion)

1.5 Generation and Recombination

Unit 2: PN Junction Diode

2.1 Physical Structure and Formation

2.2 Biasing of PN Junction

2.3 Shockley Diode Equation (Ideal Diode Equation)

Formula: I_D = I_S (e^(V_D / (n V_T)) – 1)

Where:

• I_D = diode current (A)

• I_S = reverse saturation current (A) (very small, ~10⁻¹⁵–10⁻⁹ A for Si)

• V_D = voltage across diode

• n = ideality factor (1 ≤ n ≤ 2; n=1 for ideal diffusion current; n=2 for recombination current)

• V_T = thermal voltage = kT/q ≈ 25.9 mV at 300 K (26 mV typically)

For forward bias (V_D >> V_T): I_D ≈ I_S e^(V_D/(nV_T))
For reverse bias (V_D negative, |V_D| >> V_T): I_D ≈ –I_S (reverse saturation current)

2.4 Diode Characteristics

I-V characteristic curve:

I_D (forward)
   ▲
   │                                    ┌── Exponential rise
   │                                 ┌─┘
   │                              ┌─┘
   │                           ┌─┘
   │                        ┌─┘
   │                     ┌─┘
   │                  ┌─┘
   │               ┌─┘
   │            ┌─┘
   │         ┌─┘
   │      ┌─┘
   │   ┌─┘
───┼───┘───┴───┴───┴───┴───┴───┴───┴───→ V_D
   │  Reverse (μA)
   │   leakage    (voltage axis not linear)
   │   ──────
   │   ──────
   ▼
   -I_S (small)

Key voltage points:

• Cut-in voltage (V_γ or V_F): Approx. 0.5–0.7 V for Si (significant current begins).

• Forward voltage drop (V_F): ~0.7 V for Si (at ~1-10 mA); ~0.3 V for Ge.

• Reverse breakdown voltage (V_BR): High reverse voltage where reverse current increases sharply (Zener or Avalanche breakdown).

2.5 Diode Models (for Circuit Analysis)

2.6 Capacitance in Diodes

Unit 3: Diode Circuits and Applications

3.1 Rectifiers

Key formulas (for sine wave input, resistive load):

• Average (DC) output voltage:

  • Half-wave: V_DC = V_m / π = 0.318 V_m

  • Full-wave: V_DC = 2V_m / π = 0.636 V_m

• RMS output voltage:

  • Half-wave: V_rms = V_m / 2 = 0.5 V_m

  • Full-wave: V_rms = V_m / √2 = 0.707 V_m

• Ripple factor (γ) = √( (V_rms / V_DC)² – 1 )

• Rectification efficiency (η) = P_DC / P_AC (max: 40.6% half-wave; 81.2% full-wave)

3.2 Filters (Smoothing)

3.3 Clippers (Limiters) and Clampers

3.4 Voltage Multipliers

3.5 Special-Purpose Diodes

Unit 4: Bipolar Junction Transistors (BJT)

4.1 Structure and Modes of Operation

Three regions of operation (dependent on bias voltages):

4.2 Current Relationships

Current summation: I_E = I_B + I_C (Kirchhoff’s current law applied to transistor).

4.3 BJT Configurations (Amplifier Stages)

Corrections to table for accuracy:

• Common collector (emitter follower): voltage gain ≈ 1; high input impedance; low output impedance. Used as buffer.

• Common base: low input impedance; high output impedance; current gain ≈ 1; high voltage gain; good for high frequency (due to minimal Miller effect). Base terminal is grounded for AC.

• Common emitter: moderate input and output impedance; large voltage and current gain; 180° phase inversion. Most widely used gain stage.

4.4 Biasing of BJT (Establish Q-point – DC operating point)

Goal: Set stable collector current (I_CQ) and collector-emitter voltage (V_CEQ) for linear operation (active region). Stable against variations in β, temperature, and supply voltage.

Voltage-divider bias design equations (approx):

• V_B = V_CC × (R2 / (R1 + R2))

• V_E = V_B – V_BE (≈ V_B – 0.7 V for Si)

• I_CQ ≈ I_E = V_E / R_E

• V_CEQ = V_CC – I_CQ (R_C + R_E)

4.5 Small-Signal (AC) Analysis – Hybrid-pi Model (Low Frequency)

Small-signal parameters (for CE configuration):

Hybrid-pi equivalent circuit (common emitter, low freq):

• Input: r_π between base and emitter.

• Output: current source g_m v_be (or β i_b) in parallel with r_o between collector and emitter.

4.6 BJT as a Switch

Cutoff (off): V_BE < 0.5 V (Si); I_B = 0; I_C = 0; V_CE ≈ V_CC (open switch).
Saturation (on): Sufficient I_B such that I_B > I_C(sat)/β_min; V_CE ≈ V_CE(sat) ≈ 0.1–0.3 V (closed switch).

Conditions for saturation:

• Base overdrive: I_B > I_C(sat)/β_min

• I_C(sat) ≈ (V_CC – V_CE(sat)) / R_C ≈ V_CC / R_C (if V_CE(sat) << V_CC).

Unit 5: Field Effect Transistors (FETs)

5.1 Junction Field Effect Transistor (JFET)

Regions of operation (n-channel):

JFET characteristics:

• I_DSS = drain current with V_GS = 0 (maximum current)

• V_P (or V_GS(off)) = pinch-off voltage (negative for n-channel, where channel is fully depleted, I_D = 0).

• Shockley equation (active region): I_D = I_DSS (1 – V_GS / V_P)² (for V_GS between 0 and V_P, with V_DS sufficient for pinch-off)

Advantages of JFETs over BJTs: Very high input impedance (gate is reverse biased; G-S junction has high impedance). Lower noise. Good for low-level signals. Disadvantage: Lower transconductance (g_m) compared to BJT.

5.2 Metal-Oxide-Semiconductor FET (MOSFET)

Operation of E-MOSFET (n-channel):

• Cutoff: V_GS < V_TH (threshold voltage); no channel; I_D = 0.

• Triode (linear) region: V_GS ≥ V_TH, V_DS small (<< V_GS – V_TH). I_D = K_n [2(V_GS – V_TH)V_DS – V_DS²] (Ohmic).

• Saturation (active) region: V_GS ≥ V_TH, V_DS ≥ V_GS – V_TH. I_D = K_n (V_GS – V_TH)² (saturated, independent of V_DS to first order).

Transconductance parameter (K_n): K_n = (1/2) μ_n C_ox (W/L) (process/gate geometry factor)

Power MOSFETs: High current handling; used in power supplies, motor control, switching applications (unipolar, majority carrier devices). Faster switching than BJTs.

5.3 FET Amplifiers (Basic Configurations)

Small signal parameters for FET:

• Transconductance (g_m) = ΔI_D / ΔV_GS (for JFET: g_m = g_m0 (1 – V_GS/V_P) where g_m0 = 2 I_DSS/|V_P|)

• Drain-source resistance (r_ds or r_o) = ΔV_DS / ΔI_D at constant V_GS (often large, ~100 kΩ). Reciprocal output conductance (g_ds).

Unit 6: Transistor Biasing and Stability

6.1 Concept of Stability (BJT)

Stability factors:

Stability comparison:

• Fixed bias: worst stability (very sensitive to β)

• Voltage-divider bias: best stability (all factors minimized)

• Collector-feedback bias: moderate stability.

6.2 Thermal Runaway

Definition: Positive feedback loop – increase in temperature → increase in I_CO → increase in I_C → increase in power dissipation (I_C × V_CE) → further increase in temperature → more I_C → thermal runaway (destruction).

Prevention: Proper heat sink, derating, stable biasing (voltage-divider bias with emitter resistor, or negative feedback in design). Also using emitter resistor R_E provides negative feedback.

Unit 7: Amplifier Frequency Response (Basic Concepts)

7.1 Bandwidth Definition

Gain (midband) – A_m = maximum gain (flat region).

Cutoff frequencies (f_L and f_H): Frequency where gain drops to A_m / √2 (i.e., –3 dB point). Voltage gain = A_v (dB) = 20 log₁₀ (V_out / V_in).

Bandwidth (BW) = f_H – f_L ≈ f_H (if f_L small).

Gain-bandwidth product (GBW) = |A_m| × BW (constant for many amplifiers, especially op-amps).

7.2 Low Frequency Response

Low-frequency cutoff prediction (dominant pole): Typically largest time constant dominates. f_L ≈ 1/(2π τ), where τ = R_eq × C.

7.3 High Frequency Response (BJT and FET)

Capacitances present:

Miller Effect (CE/CS configuration): Input capacitance = C_π + C_μ(1 + |A_v|). This significantly reduces input impedance at high frequency and limits bandwidth.

Unity-gain frequency (f_T, transition frequency): Frequency at which short-circuit current gain = 1 (|β| = 1 for BJT, or g_m / (2π(C_π + C_μ)) for a common-emitter configuration). Provides cutoff frequency metric.

Unit 8: Feedback Amplifiers (Introduction)

8.1 Concepts of Feedback

Negative feedback advantages:

• Gain desensitivity (gain less dependent on device parameters)

• Increased bandwidth (gain × BW product constant)

• Reduced distortion and noise

• Modified input and output impedances (depending on feedback topology)

8.2 Four Feedback Topologies

Closed-loop gain with negative feedback: A_f = A / (1 + Aβ)

• A = open-loop gain

• β = feedback factor (fraction of output fed back)

• 1 + Aβ = loop gain (desensitivity factor, improves stability by factor L)

Unit 9: Oscillators (Basic Principles)

9.1 Barkhausen Criteria for Oscillation

For sustained sinusoidal oscillations (positive feedback):

1. Loop gain magnitude: |Aβ| ≥ 1 (unity or greater)

2. Loop phase shift: ∠Aβ = 0° (or 360°) – i.e., total phase shift around loop is integer multiple of 2π rad.

Practical oscillator: Start with |Aβ| > 1 (or sufficient gain), then amplitude stabilization reduces loop gain to exactly 1 at desired amplitude (limiting, nonlinearity).

9.2 Types of Oscillators (RC and LC)

9.3 555 Timer (Astable and Monostable)

Summary Tables for Quick Review

Semiconductor Types Summary

Diode Applications Summary

Transistor Amplifier Configurations Comparison

Electrical Machines – Comprehensive Study Notes

These notes cover the fundamental principles, construction, operation, and characteristics of electrical machines, including transformers, DC machines, induction motors, and synchronous machines. Suitable for undergraduate students in electrical engineering.

Part 1: Fundamentals of Electromechanical Energy Conversion

1.1 Basic Principles

Electrical machines operate on two fundamental electromagnetic principles:

Faraday’s Law of Electromagnetic Induction: The induced electromotive force (EMF) in a closed circuit is equal to the negative rate of change of magnetic flux linkage through the circuit.

e=−Ndϕdte=−Ndtdϕ​

where:

• $e$ = induced EMF (volts)

• $N$ = number of turns

• $\varphi$ = magnetic flux (webers)

Lenz’s Law: The direction of induced EMF is such that it opposes the change in flux that produced it.

Lorentz Force Law (Motor Action): A current-carrying conductor in a magnetic field experiences a force.

$$F=BIl\sin \theta$$

where:

• $F$ = force (newtons)

• $B$ = magnetic flux density (tesla)

• $I$ = current (amperes)

• $l$ = length of conductor in magnetic field (meters)

• $\theta$ = angle between current direction and magnetic field

1.2 Magnetic Circuits

Ohm’s Law for Magnetic Circuits:

$$\mathcal{F}=\varphi \mathcal{R}$$

or

NI=ϕ×lμANI=ϕ×μAl​

1.3 Hysteresis and Eddy Current Losses

Core Losses (Iron Losses) occur in magnetic materials subjected to alternating flux:

Steinmetz Equation for Hysteresis Loss:

Ph=khfBmnPh​=kh​fBmn​

where khkh​ is hysteresis coefficient, $f$ is frequency, BmBm​ is maximum flux density, $n$ ≈ 1.5-2.5

Eddy Current Loss:

Pe=kef2Bm2Pe​=ke​f2Bm2​

where keke​ is eddy current coefficient

1.4 Torque Production

The torque produced by an electrical machine is given by:

T=kϕIaT=kϕIa​

where:

• $T$ = torque (N·m)

• $k$ = machine constant

• $\varphi$ = flux per pole

• IaIa​ = armature current

For a DC machine:

T=P2πnT=2πnP​

where $P$ is mechanical power (watts), $n$ is speed (revolutions per second)

Part 2: Transformers

2.1 Introduction and Principle of Operation

A transformer is a static electrical device that transfers electrical energy from one circuit to another through electromagnetic induction, typically changing voltage levels.

Basic Principle: A time-varying current in the primary winding produces a time-varying magnetic flux in the core, which induces an EMF in the secondary winding.

Faraday’s Law Applied:

Ep=Npdϕdt,Es=NsdϕdtEp​=Np​dtdϕ​,Es​=Ns​dtdϕ​

2.2 Voltage and Current Relationships

Ideal Transformer (No losses, perfect coupling):

Step-up Transformer: Ns>NpNs​>Np​, Vs>VpVs​>Vp​, Is<IpIs​<Ip​

Step-down Transformer: Ns<NpNs​<Np​, Vs<VpVs​<Vp​, Is>IpIs​>Ip​

2.3 Transformer Construction

Core Types:

• Core-type: Windings surround the core

• Shell-type: Core surrounds the windings

2.4 Equivalent Circuit of a Practical Transformer

Non-ideal effects accounted for:

• Rp,RsRp​,Rs​: Winding resistances (copper losses)

• Xp,XsXp​,Xs​: Leakage reactances (flux that doesn’t link both windings)

• RcRc​: Core loss resistance (hysteresis + eddy currents)

• XmXm​: Magnetizing reactance (flux that links both windings)

Approximate Equivalent Circuit Referred to Primary:

Req=Rp+a2RsReq​=Rp​+a2Rs​Xeq=Xp+a2XsXeq​=Xp​+a2Xs​

where a=Np/Nsa=Np​/Ns​

2.5 Voltage Regulation

Definition: The change in secondary voltage from no-load to full-load, expressed as a percentage of full-load voltage.

Voltage Regulation=Vnl−VflVfl×100%Voltage Regulation=Vfl​Vnl​−Vfl​​×100%

where VnlVnl​ = no-load secondary voltage, VflVfl​ = full-load secondary voltage

2.6 Transformer Losses and Efficiency

Efficiency:

η=PoutPin=PoutPout+Pcu+Pcη=Pin​Pout​​=Pout​+Pcu​+Pc​Pout​​

Maximum Efficiency Condition: Copper loss = Core loss

I2Req=PcI2Req​=Pc​

2.7 Transformer Tests